# 17-Registers - Registers Today well see another common...

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Registers 1 Registers Today we’ll see another common sequential device: registers. They’re a good example of sequential analysis and design. They are also frequently used in building larger sequential circuits. Registers hold larger quantities of data than individual flip-flops. Registers are central to the design of modern processors. There are many different kinds of registers. We’ll show some applications of these special registers.

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Registers 2 What good are registers? Flip-flops are limited because they can store only one bit. We had to use two flip-flops for our two-bit counter examples. Most computers work with integers and single-precision floating- point numbers that are 32-bits long. A register is an extension of a flip-flop that can store multiple bits. Registers are commonly used as temporary storage in a processor. They are faster and more convenient than main memory. More registers can help speed up complex calculations. We’ll discuss RAM next time, and later we’ll also see how registers are used in designing and programming CPUs.
Registers 3 A basic register Basic registers are easy to build. We can store multiple bits just by putting a bunch of flip-flops together! A 4-bit register from LogicWorks, Reg-4 , is on the right, and its internal implementation is below. This register uses D flip-flops, so it’s easy to store data without worrying about flip-flop input equations. All the flip-flops share a common CLK and CLR signal.

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Registers 4 Adding a parallel load operation The input D 3 -D 0 is copied to the output Q 3 -Q 0 on every clock cycle. How can we store the current value for more than one cycle? Let’s add a load input signal LD to the register. If LD = 0 , the register keeps its current contents. If LD = 1 , the register stores a new value, taken from inputs D 3 -D 0 . LD Q(t+1) 0 Q(t) 1 D 3 -D 0
Registers 5 Clock gating We could implement the load ability by playing games with the CLK input, as shown below. When LD = 0 , the flip-flop C inputs are held at 1. There is no positive clock edge, so the flip-flops keep their current values. When LD = 1 , the CLK input passes through the OR gate, so the flip- flops can receive a positive clock edge and can load a new value from the D 3 -D 0 inputs.

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Registers 6 Clock gating is bad This is called clock gating , since gates are added to the clock signal. There are timing problems similar to those of latches. Here, LD must be
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## This note was uploaded on 10/19/2011 for the course CS 231 taught by Professor - during the Spring '08 term at University of Illinois at Urbana–Champaign.

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17-Registers - Registers Today well see another common...

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