Lec-02_Scaling-MOS-Models-a

Lec-02_Scaling-MOS-Models-a - EE M216A .:. Fall 2010...

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EE M216A .:. Fall 2010 Lecture 2 Scaling, MOS Transistor Models Prof. Dejan Markovi ć ee216a@gmail.com Announcements ± Homework #1 will be posted by Friday Due Fri, Oct 9, 5pm ± Your classwik accounts (216a group) have been activated Your classwiki accounts (216a group) have been activated 23 students have signed up so far (~20 missing) Please spread the word around (for those who didn’t come to class / didn’t put their e mail on the class mailing list on EEweb) ± Today’s lecture Technology scaling D. Markovic / Slide 2 MOS transistor modeling EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 2
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Technology Scaling is Power Driven 1970 1985 2000 ± Bipolar Æ NMOS Æ CMOS Æ ??? power wall power wall power wall ± System performance has benefited from higher integration ± In the mid 80’s, CMOS displaced NMOS technologies to address power dissipation CMOS delivered better cost performance since it was more energy efficient and improved the integration level At that time CMOS was on the horizon ± Replacing CMOS by another more energy efficient technology is a D. Markovic / Slide 3 Replacing CMOS by another more energy efficient technology is a distant prospect now Low power high speed CMOS technology is becoming an indispensable, rather than desirable, technology Power is the main challenge we need to address EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 3 The Limits Theoretical Practical ± System ± Ci i Circuit ± Device ± Material Theoretical limits: physics Practical limits: + manufacturing cost D. Markovic / Slide 4 ± Fundamental [J. Meindl, Proc. IEEE, 1995] EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 4
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Circuit Limits ± #1: logic levels (gain) ± #2: energy/transition ± #3: delay ± #4: global interconnect D. Markovic / Slide 5 EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 5 Circuit Limit #1: Logic Levels (Gain) ± Distinguish logic 0’s from 1’s (restore logic levels Æ |gain| >1) D. Markovic / Slide 6 [J. Meindl, Proc. IEEE, 1995] EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 6
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Circuit Limits (Cont.) ± #2: Energy/transition Neglecting static current ± #3: Delay Limited by ± #4 Gl b l i t D. Markovic / Slide 7 #4: Global interconnect Interconnect delay should not exceed gate delay EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 7 Practical Limits ± Scaling towards fundamental limits ~130nm is the most cost effective technology (the last generation for which deep UV microlithography will suffice) D. Markovic / Slide 8 [J. Meindl, Proc. IEEE, 1995] EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 8
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Practical Limits (Cont.) ± Metric: chip size D = 40mm D = 50mm (16” wafer) (12” wafer) D = 25mm (8” wafer) D. Markovic / Slide 9 [J. Meindl, Proc. IEEE, 1995] EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 9 Practical Limits (Cont.) ± Packing efficiency = # transistors / min feature area 3D / vertical integration Layout density # mask levels D. Markovic / Slide 10 [J. Meindl, Proc. IEEE, 1995] EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 10
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Basic Scaling Trends 10000 Const V DD Const E
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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Lec-02_Scaling-MOS-Models-a - EE M216A .:. Fall 2010...

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