Lec-03_Delay-Models-a

# Lec-03_Delay-Models-a - EE M216A .:. Fall 2010 Lecture 3...

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EE M216A .:. Fall 2010 Lecture 3 Delay Models Prof. Dejan Markovi ć [email protected] Gate Delay ± Gate delay is a measure of time between an input transition and an output transition May have different delays for different input to output paths Different for an upward or downward transition t pLH – propagation delay from LOW to HIGH (of the output) Logic Gates Inputs Outputs D. Markovic / Slide 2 ± A transition is defined as the time at which a signal crosses a logical threshold voltage Digital abstraction for 1 and 0 Often use V DD /2 EEM216A .:. Fall 2010 Lecture 3: Delay Models | 2

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Static CMOS Gate Delay ± Output of a gate drives the inputs to other gates (and wires) Only pull up or pull down, not both Capacitive loads in o V M t pHL out out in in t PD1 t PD2 C LOAD ± The delay of EACH stage is treated separately D. Markovic / Slide 3 out t PD = t PD1 + t PD2 ± Transition moment is defined at V M (logical threshold) EEM216A .:. Fall 2010 Lecture 3: Delay Models | 3 Voltage Transfer Characteristics (VTC) ± Characterize the DC response of a simple inverter ± 5 Regions of operation in out W N /L N W P /L P V in <V TN , V out =V DD , N Off, P Lin V in >V TN , V out >V in V TP N Sat, P Lin V in >V TN , V in V TP >V out >V in V TN N Sat, P Sat V in <V DD +V TP , V in V TN >V out N Lin P Sa V out P:Lin P:Lin N:Sat P:Sat V M D. Markovic / Slide 4 N Lin, P Sat V in > V DD +V TP , V out =V GND , N Lin, P Off ± Logical threshold When V in = V out V in N:Off N:Sat P:Sat N:Lin P:Off N:Lin EEM216A .:. Fall 2010 Lecture 3: Delay Models | 4
Logical Threshold Voltage ± Set I DSATP = I DSATN and solve Dependence on P:N sizing and mobility ratio Slight dependence on V in out W /L W P /L P in 1 W P1 W P2 in 2 TP/N ± Not so easy if not an inverter Depends on which input the gate is driving In 1 to Out transfer characteristic can be V out V M W N /L N out W N1 in 1 W N2 in 2 D. Markovic / Slide 5 different from In 2 to Out Use V DD /2 as average case Unless severely skew the P:N ratio EEM216A .:. Fall 2010 Lecture 3: Delay Models | 5 V in 0 2 2 = + DSATp Tp DD M DSATp p DSATn Tn M DSATn n V V V V V k V V V V k Calculating V M 12 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) r V V V r V V V DSATp Tp DD DSATn Tn M + + + + + = 1 2 2 n satn p satp DSATn n DSATp p W W V k V k r = = υ D. Markovic / Slide 6 10 0 10 1 0.8 0.9 1 1.1 1.2 W p /W n High V DD : Long L or low V DD : EEM216A .:. Fall 2010 Lecture 3: Delay Models | 6

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Sensitivity of VTC to P:N ± Fortunately, the logical threshold is not very sensitive to P:N ratio Ranges from 1.35V to 1.75V (for a 3.3 V V DD ) V /2 is quite reasonable DD D. Markovic / Slide 7 EEM216A .:. Fall 2010 Lecture 3: Delay Models | 7 V in 50% 2 pHL pLH p t t t + = Delay Definitions V out t pHL t pLH t 90% D. Markovic / Slide 8 t f t r t 10% 50% EEM216A .:. Fall 2010 Lecture 3: Delay Models | 8
RC Model ±

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## This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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Lec-03_Delay-Models-a - EE M216A .:. Fall 2010 Lecture 3...

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