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Lec-04_Speed-Optimization-a

# Lec-04_Speed-Optimization-a - EE M216A Fall 2010 Lecture 4...

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EE M216A .:. Fall 2010 Lecture 4 Speed Optimization Prof. Dejan Markovi ć [email protected] Speed Optimization via Gate Sizing Gate sizing basics P:N ratio Complex gates V l it t ti Velocity saturation Tapering Developing intuition Number of stages vs. fanout Popular inverter chain example D. Markovic / Slide 2 Formal approach: logical effort Sizing optimization for speed EEM216A .:. Fall 2010 Lecture 4: Speed Optimization | 2

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Basic Gate Sizing Relationships Rise and fall delays are determined by the pull up and pull down “strength” Besides the dimensions, strength depends on µ , C OX , V T PMOS is weaker because of lower µ PMOS is weaker because of lower P Larger P network than N network Increasing size of gate can reduce delay Inverse (1/W) relationship with resistance (and hence delay) BUT it can slow down the gate driving it Proportional (W) relationship with Capacitance So be careful! D. Markovic / Slide 3 Proportional (W) relationship with Capacitance. So be careful! EEM216A .:. Fall 2010 Lecture 4: Speed Optimization | 3 P:N Ratio for “Equal” Rise and Fall Delay Good to have roughly equal delays for different transitions Don’t need to worry about a worst case sequence Size P’s to compensate for mobility C V L hl th OX , V T , L are roughly the same Make the Pull up and Pull down resistances equal R N /R P = 1 = µ P W P / µ N W N = k β, k = mobility ratio, β = P:N ratio W P /W N = µ N / µ P W I R DRV µ / 1 / 1 D. Markovic / Slide 4 Approximately the same as making V THL = V DD /2 Easy for an inverter What about more complex gates? EEM216A .:. Fall 2010 Lecture 4: Speed Optimization | 4
Complex Gate Sizing N stack series devices need N times lower resistance N × Width Make worst case strength of each path equal Multi input transition can result in stronger network Multi input transition can result in stronger network Long series stacking is VERY bad W 2W 2W 6W 6W B A 6W E.g.: β = 2 D. Markovic / Slide 5 C W W W B A C W W W EEM216A .:. Fall 2010 Lecture 4: Speed Optimization | 5 Accounting for Velocity Saturation Series stacking is actually less velocity saturated If we use R no_stack = (4/3)R stack Adjust the single device size to account for velocity saturation W 2W 2W 6W 6W B A 6W E.g.: β = 2 4W/3 4W/3 D. Markovic / Slide 6 C W W W B A C W W W EEM216A .:. Fall 2010 Lecture 4: Speed Optimization | 6

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P:N Ratio for Minimum Delay Delay of an inverter chain (2 inverters) to include t pLH & t pHL W P W P W W in out W P W Let R PDRV ~ R 0 ’/W P µ P , R NDRV ~ R 0 ’/W N µ N , C G ~ C 0 (1+W P /W N ) t PD = t D1 + t D2 = R 0 ’(1/W P µ P + 1/W N µ N ) C 0 (1+W P /W N ) τ N (1+1/k β )(1+ β ) Min(t PD ): dt PD /d β = 0 = τ N (1 k/ β 2 ) N N N D. Markovic / Slide 7 So β = W P /W N = sqrt( µ N / µ P ) Intuition is that since NMOS has more drive for a given size, it is better to use more NMOS EEM216A .:. Fall 2010 Lecture 4: Speed Optimization | 7 FO4 Inverter Delay vs. P:N Ratio β Optimal β = sqrt( µ ) for minimum delay Curve is relatively flat so not a strong delay tradeoff 4 inverter delay ( τ ) D. Markovic
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