Lec-05_Logical-Effort-a

Lec-05_Logical-Effort-a - EE M216A Fall 2010 Lecture 5...

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EE M216A .:. Fall 2010 Lecture 5 Logical Effort Prof. Dejan Markovi ć [email protected] Logical Effort Recap Normalized delay d = g · h + p g is the logical effort of the gate g C / C = IN INV Inverter is sized such that R INV equals the gate’s drive strength h is the electrical effort h = C OUT / C IN The combination of g · h is essentially our fan out definition p is the parasitic effort p = C SELF / C INV D. Markovic / Slide 2 Typically ~1 for an inverter May have different g , p for each type of gate structure The g , p may differ per input, and for pull up/down EEM216A .:. Fall 2010 Lecture 5: Logical Effort | 2
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A Side Note: Total Gate Effort ( g TOT ) One way of evaluating a gate is to look at the total logical effort of the gate g TOT = C IN_TOT / C INV A sum of the total input capacitance Example: 3 input NAND Equivalent inverter is 4:2 g INPUT = 10/6=5/3 g TOT = 30/6 = 5 (or 3·g INPUT ) W P : W N = 4:6 D. Markovic / Slide 3 The total gate effort is not very useful to calculate delay But it is an indication of the “cost” of the gate Can be very useful in gate mapping of logic synthesis To find which gate is best to use to map a given Boolean expression EEM216A .:. Fall 2010 Lecture 5: Logical Effort | 3 A Note on Asymmetry The gates used in examples so far have been symmetric All inputs are essentially identical Some are bundled P:N ratio is approximately equal to the mobility ratio Same as the reference inverter The truth is that inputs of most gates are not symmetric Different inputs may see different capacitances Even series stacked gates may not be the same size Pull up and pull down is rarely equal resistance C ll thi “ k d” t D. Markovic / Slide 4 Call this “skewed” gates P:N sizing for optimal delay is β = root( µ ) Inverter in a domino gate often favors the PMOS to improve speed EEM216A .:. Fall 2010 Lecture 5: Logical Effort | 4
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Asymmetric Examples PMOS NOR: different sizing Equivalent inv is still 6:2 C inA = 10, C inB = 26 (10/8 5/4) t l t For more complex gates: Equivalent inv is now 9:3 g EDC =21/12=7/4 , g 30/12 5/2 g A (10/8=5/4) not equal to g B (26/8=13/4) B input is much worse… (for a reason) B d e a’ b’ c d e 24 12 12 18 18 9 9 9 A’B’ =30/12=5/2 D. Markovic / Slide 5 A NOR Output b’ a’ c 8 2 2 12 12 12 Same β = µ = 3 The larger g is BAD! (More effort to do logic) EEM216A .:. Fall 2010 Lecture 5: Logical Effort | 5 What is the Reference Inverter? The assumption of logical effort is that the reference inverter has equal rise and fall delays β = µ The implication for different pull up and pull down resistance is that the rising and falling delays are not equal Similar to the parasitic delay calculation earlier d UP = g UP · h + p UP d DN = g DN · h + p DN D. Markovic / Slide 6 Since static CMOS gates are inverting, the transitions through subsequent gates must be alternating Use an average logical effort (and parasitic effort) – a good idea g AVG = ( g UP + g DN )/2 EEM216A .:. Fall 2010
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