Lec-06-Logic-Design-Opt-a2

Lec-06-Logic-Design- - EEM216A Fall 2008 Lecture 6 Logic Design and Optimization Dejan Markovic [email protected] Logic Families Static CMOS logic

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Logic Design and Optimization EEM216A – Fall 2008 Lecture 6 Dejan Markovic [email protected] EEM216A / Fall 2008 D. Markovic / Slide 2 Logic Families ± Static CMOS logic ± Pass-transistor logic ± Dynamic logic
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EEM216A / Fall 2008 D. Markovic / Slide 3 Static CMOS V DD F(In 1 ,In 2 ,…In N ) In 1 In 2 In N In 1 In 2 In N PUN PDN PMOS only NMOS only ± PUN and PDN are dual logic networks ± PUN and PDN functions are complementary EEM216A / Fall 2008 D. Markovic / Slide 4 Y = X if A AND B Y = X if A OR B ± Transistor switch controlled by its gate signal NMOS switch closes when switch control input is high ± NMOS transistors pass a “strong” 0 but a “weak” 1 AB XY A B AND OR NMOS in Series/Parallel Connection
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EEM216A / Fall 2008 D. Markovic / Slide 5 ± PMOS switch closes when switch control is low ± PMOS transistors pass a “strong” 1 but a “weak” 0 XY AB A B NOR NAND Y = X if A AND B = A + B Y = X if A OR B = AB PMOS in Series/Parallel Connection EEM216A / Fall 2008 D. Markovic / Slide 6 CMOS Transistor Switch Model ± They are not ideal switches! Adjust for the impact of V T ± NMOS connected when gate is high high output is degraded ± PMOS connected when gate is low low output is degraded Vdd -Vth Gnd Vdd - Vth weak strong weak strong
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EEM216A / Fall 2008 D. Markovic / Slide 7 CMOS Logic Style ± PUP is the dual to PDN (can be shown using DeMorgan’s Theorems) ± The complementary gate is inverting A + B = AB AB = A + B AND = NAND + INV EEM216A / Fall 2008 D. Markovic / Slide 8 Example: NAND Gate ± PDN: G = AB Conduction to GND ± PUN: F = A + B = AB Conduction to V DD ± G(In 1 ,In 2 ,In 3 ,…) F(In 1 ,In 2 ,In 3 ,…)
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EEM216A / Fall 2008 D. Markovic / Slide 9 Complex CMOS Gate OUT = D + A • (B + C) D A BC D A B C EEM216A / Fall 2008 D. Markovic / Slide 10 C (a) pull-down network SN1 SN4 SN2 SN3 D F F A D B C D F A B C (b) Deriving the pull-up network hierarchically by identifying sub-nets D A A B C V DD V DD B (c) complete gate Constructing a Complex Gate
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EEM216A / Fall 2008 D. Markovic / Slide 11 Logic Families ± Static CMOS logic ± Pass-transistor logic ± Dynamic logic EEM216A / Fall 2008 D. Markovic / Slide 12 Quiz: Final Voltage ± |V T | = 0.5V, V DD = 2.5V V o =0 1.5 2 V o =0 2 1.5 V o =2.5 1.25V 1.5 V o =0 2.5 2.25 V o =2.5 1.0 0.0 1.0 V o =2.5 V o =0 V o =2.5
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EEM216A / Fall 2008 D. Markovic / Slide 13 Pass Transistor Logic (PTL) Switch Network Out Out A B B B Inputs ± N transistors ± No static power consumption Allows primary inputs to drive S and D terminals! (idea: reduce the number of transistors) EEM216A / Fall 2008 D. Markovic / Slide 14 Example: AND Gate B B A F = AB 0 ABF 000 010 100 111
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EEM216A / Fall 2008 D. Markovic / Slide 15 A = 2.5 V B C = 2.5V C L A = 2.5 V C = 2.5 V B M 2 M 1 M n NMOS-only Switch ± V B does not pull up to V DD , but to V DD –V Tn Threshold voltage loss causes static power consumption
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.