Lec-07_Leakage-Power-a

Lec-07_Leakage-Power-a - EE M216A .:. Fall 2010 Lecture 7...

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EE M216A .:. Fall 2010 Lecture 7 Leakage Power Prof. Dejan Markovi ć [email protected] ± Standby Power Reduction Longer channels Outline Stack effect / complex gates Multiple thresholds Sleep transistors D. Markovic / Slide 2 Variable threshold CMOS EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 2
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Power/Energy Optimization Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Sleep Mode Run Time Active Logic design Scaled V DD T Sizing Multi V DD Clock Gating DFS, DVS D. Markovic / Slide 3 Leakage Stack effects + Multi V T Sleep T’s Multi V DD Var. V T + Input control + Variable V T EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 3 1.2 120 2 P The Leakage Challenge ± V TH scaling has to slow down to avoid exp power increase 0.2 0.4 0.6 0.8 1 20 40 60 80 100 Technology node[nm] Voltage [V] V TH V DD Technology node 1 P LEAK Power [μW / gate] Subthreshold leak (Active leakage) D. Markovic / Slide 4 Year 2002 ’04 ’06 ’08 ’10 ’12 ’14 ’16 0 0 2002 ’04 ’06 ’08 ’10 ’12 ’14 ’16 0 Year DYNAMIC [T. Sakurai, ISSCC 03] EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 4
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The Leakage Challenge (Cont.) ± 130nm data (getting worse with scaling) 1.4 y Source: S. Borkar (Intel) 30% Frequency ~30% Leakage Power ~5 10X 1.1 1.2 1.3 rmalized Frequenc D. Markovic / Slide 5 EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 5 5X 0.9 1.0 12345 Normalized Leakage N o 08 1 V ref -180mV Flip Side: Leakage is Good for You! ± Set V TH , find V DD to minimize energy for a fixed performance 0.2 0.4 0.6 0.8 E Op / nominal E re f nominal th 0.81V dd max V th ref -95mV 0.57V dd V th ref -140mV Optimal designs have high leakage (E Lk /E Sw 0.5) D. Markovic / Slide 6 10 -2 10 -1 10 0 10 1 0 E Leakage /E Switching parallel pipeline 0.52V dd Must adapt to process variations and activity EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 6
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± Design time techniques Transistor level multi V TH design Stack effect Working with Leakage Gate level/Synthesis approaches ± Standby/runtime leakage control MTCMOS/power down Substrate bias (VTCMOS) Self substrate bias (SSB) D. Markovic / Slide 7 Self adjusting threshold voltage (SAT) Standby power reduction (SPR) SAT+SPR EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 7 ± Using higher thresholds Channel doping Body biasing St k d d i Reducing Leakage Stacked devices ± Using longer transistors Limited benefit Increase in active current D. Markovic / Slide 8 ± Reducing the voltage!! EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 8
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Longer Channels (Old Days) 35% 5 6 7 8 nt [nA] Leakage current (130nm technology) ± 10% longer gates reduce leakage by 10% L nom 0 1 2 3 4 0.1 0.15 0.2 0.25 0.3 Gate Length [mm Leakage Curr e Switching energy 35% ± Increases switching power by 21% with W / L = const D. Markovic / Slide 9 Gate Length [mm] ± Doubling L reduces leakage by 3x ± Impacts performance Attractive when don’t have to increase W (e.g. memory) EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 9 Stack Effect ± Transistor stacks greatly reduce leakage NAND gate D. Markovic / Slide 10 EEM216A .:. Fall 2010 Lecture 7: Leakage Power | 10 Leakage power reduction [IEEE Press, New York, 2000]
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Stack Effect ±
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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Lec-07_Leakage-Power-a - EE M216A .:. Fall 2010 Lecture 7...

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