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EE M216A .:. Fall 2010
Lecture 8
Energy
‐
Delay Optimization
Prof. Dejan Markovi
ć
ee216a@gmail.com
Some Common Questions
±
Is sizing better than
V
DD
for energy reduction?
±
What are the optimal values of gate size and
V
DD
?
±
What is the optimal ratio of leakage / switching for min
E
?
±
Shall we increase or decrease
V
DD
for energy reduction?
±
What is the optimal circuit topology?
D. Markovic
/
Slide 2
±
How many levels of parallelism is good?
±
Etc.
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 2

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*Sign up*Energy Minimization Problem
±
Goal: achieve the lowest energy under the delay constraint
Unoptimized
Energy
Unoptimized
design
W
V
DD
W
&
V
DD
E
max
E
D. Markovic
/
Slide 3
Delay
W
&
V
DD
&
V
TH
D
max
D
min
min
(f
clk
max
)
(f
clk
min
)
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 3
Energy
‐
Delay Sensitivity
±
Slope of E
‐
D curve around a design point (e.g. (
A
0
,
B
0
))
∂
E
/
∂
A
S
=
∂
D
/
∂
A
A
=
A
0
A
S
B
S
A
f
(
A
,
B
0
)
Energy
(
A
0
,
B
0
)
D. Markovic
/
Slide 4
[D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, JSSC, Aug’04]
f
(
A
0
,
B
)
Delay
D
0
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 4

Solution: Equal Sensitivities
±
A fixed point is reached when all sensitivities are equal
∆
E
=
S
A
·(
−∆
D
)+
S
B
·
∆
D
A B
f
(
A
,
B
0
)
Energy
(
A
0
,
B
0
)
∆
D
f
(
A
1
,
B
)
D. Markovic
/
Slide 5
f
(
A
0
,
B
)
Delay
D
0
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 5
Circuit Optimization
topology
A
topology
B
Energy/op
Constraints
D. Markovic
/
Slide 6
±
Reference design
−
D
min
sizing @
V
DD
max
,
V
TH
ref
Delay
Goal:
find optimal
E
‐
D
tradeoff for a
logic function
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 6

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*Sign up*Alpha
‐
power based Delay Model
Combined with Logical Effort Formulation (*)
1.5
2
2.5
3
3.5
4
delay (norm.)
V
on
= 0.37 V
α
d
= 1.53
simulation
model
±
Fitting parameters
−
V
on
,
α
d
,
K
d
±
Effective fanout
−
D. Markovic
/
Slide 7
0.5
0.6
0.7
0.8
0.9
1
0
0.5
1
V
dd
/ V
dd
ref
FO
4
(*) [Sutherland et al., Logical Effort, 1999]
V
DD
ref
= 1.2V, FO4 (
V
DD
ref
) = 25ps
.
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 7
Energy Model
±
Switching energy
±
Leakage energy
D. Markovic
/
Slide 8
with:
D
: the cycle time
I
0
(
S
in
)
: normalized leakage current with inputs in state
S
in
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 8

Adjusting Switching Energy of a Gate
,
dd i
V
,1
dd i
V
+
i
i
+1
W
wire
p
nom,i
W
i
W
i
W
i+1
W
i
W
par,i
W
out
Sizing
Supply
D. Markovic
/
Slide 9
= energy stored on the logic gate
i
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 9
Optimization Setup
±
Reference/nominal circuit
–
Sized for
D
min
@
V
DD
nom
±
Df
i dl
t i
ergy
reference
Define delay constraint
–
D
con
=
D
min
(1 +
d
inc
/100)
±
Minimize energy under delay constraint
–
V
DD
scaling (global, discrete, per
‐
stage)
–
Gate sizing (
W
)
D
min
Delay
E
n
D. Markovic
/
Slide 10
–
Threshold adjustment (
V
TH
)
–
Optional buffering
EEM216A .:. Fall 2010
Lecture 8: Energy
‐
Delay Optimization | 10

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