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EE M216A .:. Fall 2010 Lecture 9 Adders Prof. Dejan Markovi ć [email protected] ± Basic terminology ± Adder building blocks Today: Adders ± Basic adder topologies Linear adders (n < 16) Fast parallel adders (n > 16) ± Some examples D. Markovic / Slide 2 EEM216A .:. Fall 2010 Lecture 9: Adders | 2

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32 Bit ALU Architecture ± Many ALUs clustered in the execution core: high power density Shift control Mux control Courtesy: R Krishnamurth Adder core Sum 2:1 External operands 5:1 Mux 6: 1 O/p Mux 6:1 Mux External operands R. Krishnamurthy (Intel) D. Markovic / Slide 3 EEM216A .:. Fall 2010 Lecture 9: Adders | 3 Loopback bus Mux Mux Mux control Sign control ALUs are Thermal Hotspots ± ALUs: performance and peak current limiters ± Goal: high performance energy efficient design Processor thermal map Execution core Cache Integer Temp ( o C) D. Markovic / Slide 4 EEM216A .:. Fall 2010 Lecture 9: Adders | 4 and FP ALUs and MACs Courtesy: R. Krishnamurthy (Intel)

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Full Adder: Logic Implementation (3 2 Adder) ± Sum function S o =1 when Odd input 1’s S o = XOR(A,B,C i ) ABC i S o C o 00000 00110 0 1 0 S o = A x B x C i ± Carry function C o =1 when 2 or more input 1’s C o = Majority(A,B,C i ) C o = AB+BC i +AC i A B 1 0 01101 10010 10101 11001 11111 D. Markovic / Slide 7 Full adder Sum C out C in SA B C i ⊕⊕ = A =B C i i i +++ C o AB BC i AC i ++ = Binary Adder EEM216A .:. Fall 2010 Lecture 9: Adders | 7 Basic Architecture: Ripple Carry Adder Hal Ful A 0 B 0 C 1 A 1 B 1 C 2 Ful A n-1 B n-1 C n C n 1 ± Sum is calculated starting at LSB Carry “ripples” from LSB into higher order bits to compute the Half Adder Full Adder S 0 S 1 Full Adder S n-1 n-1 D. Markovic / Slide 8 sums and generate the next carry ± Max delay t delay = t sum + (N 1) t carry EEM216A .:. Fall 2010 Lecture 9: Adders | 8
Complementary Static CMOS Full Adder ± Implement as separate gates… Not as efficient (especially XOR) ± Generate carry first (longer critical path) ABC i S o C o 00000 001 1 0 010 1 0 Use carry to generate sum AB B A C i X V DD V DD C i B A A B C i V DD 0110 1 100 1 0 1010 1 1100 1 111 11 = C o D. Markovic / Slide 9 EEM216A .:. Fall 2010 Lecture 9: Adders | 9 28 Transistors C i A A BB V DD C i A B A C i B C o S Layout Considerations ± Design each adder so that they can easily stack A 0 B 0 A B S 0 S 1 C 0 C 1 Embed wiring into design ± Use a single cell Can’t share V DD and V GND ± 2 bits per slice to share A 1 B 1 A 0

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