Lec-10_Latches-and-FFs-a

Lec-10_Latches-and-FFs-a - EE M216A .:. Fall 2010 Lecture...

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EE M216A .:. Fall 2010 Lecture 10 Latches and Flip Flops Prof. Dejan Markovi ć ee216a@gmail.com Brief Introduction to Clocking / Latches & FFs ± Means to synchronize By allowing events to happen at known timing boundaries, we can sequence these events ± Greatly eases building of FSMs Clock strobe indicates the moment when states are stored ± No need to worry about variable delay through the CL All signals are delayed until the clock edge (clock imposes the worst case delay) Dataflow FSM D. Markovic / Slide 2 register Comb Logic Comb Logic Lecture 10: Latches and Flip Flops | 2 EEM216A .:. Fall 2010
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Positive Feedback: Bi Stability ± State storage V i1 V o2 V o1 =V i2 V o1 V o1 =V i2 V V i1 A V o2 V =V D. Markovic / Slide 3 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 3 C B V i1 =V o2 o1 i2 Meta Stability ± Gain should be larger than 1 in the transition region A V o1 =V i2 C D. Markovic / Slide 4 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 4 B V i1 =V o2 δ V
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Writing into a Static Latch ± Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states CLK CLK D Q D CLK CLK D D. Markovic / Slide 5 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 5 CLK Converting into a MUX Forcing the state Storage Mechanisms CLK CLK D CLK Q CLK CLK D Q D. Markovic / Slide 6 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 6 Dynamic Static
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Pseudo Static Latch CLK CLK D CLK D D CLK Q D. Markovic / Slide 7 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 7 Dynamic Pseudo static Latch versus Register ± Latch: level sensitive Clk low: hold mode Clk high: transparent ± Register: edge triggered Stores on the Clk edge (rising, falling, both) D Clk Q D Clk Q Clk Clk D. Markovic / Slide 8 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 8 D D QQ
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Transmission Gate Latches Simplest implementation Basic static latch Complete implementation ± Only 4 transistors ± Pull up/down keeper ± Feedback turned off (a) (c) Clk D Q Q S (b) Q S S Clk D Clk D D. Markovic / Slide 9 ± Dynamic when S = 1 ± Susceptible to noise EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 9 ± Conflict at node S when writing new D when writing ± No conflict ± Larger Clk load From: Oklobdzija et al., Wiley 2003 Cross Coupled NAND ± This circuit is not used in datapaths anymore, but it is a basic building memory cell Added clock S Q R Q M M 2 M M 4 Q M 6 CLK M 8 CLK V DD Q D. Markovic / Slide 10 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 10 1 3 M 5 S M 7 R
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Principal Ways to Build a Register ± Registers (flip flops) are built from latches Master slave Pulse triggered D Clk Q D Clk Q Clk D D Clk Q Clk D L 1 L 2 L D. Markovic / Slide 11 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 11 Master Slave Latches Pulse Triggered Latch Characterizing Timing ± Propagation delay (assumes that setup/hold are satisfied) t D Q D Clk Q D Clk Q t Clk Q t Clk Q D. Markovic / Slide 12 EEM216A .:. Fall 2010 Lecture 10: Latches and Flip Flops | 12 Latch Register Clk Q Clk Q
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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Lec-10_Latches-and-FFs-a - EE M216A .:. Fall 2010 Lecture...

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