Lec-11_Timing-a

# Lec-11_Timing-a - EE M216A Fall 2010 Lecture 11 Timing...

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EE M216A .:. Fall 2010 Lecture 11 Timing Analysis Prof. Dejan Markovi ć Two Types of Machines with State (Storage) Two quite different abstract models: Data storage used for computation (Data Flows) ± The storage is used to hold data that is being manipulated. In this model the number of bits of state can be enormous but it does model the number of bits of state can be enormous, but it does not matter. It is simply the data set that is being manipulated. ± State is not that important, it is the flow of data that is critical. States for sequencing information (Finite State Machines) ± In this abstraction, the storage is used to hold your place in some decision making process. It indicates where you are, and using thi i f ti d id h t t d t D. Markovic / Slide 2 this information you decide what to do next. ± The amount of state (number of unique decision points) is finite, and usually limited. One could think about drawing out the ‘decision graph’ showing the possible transitions between states. Lecture 11: Timing Analysis | 2 EEM216A .:. Fall 2010

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Timing Analysis ± Timing constraints Long path: Cycle time / setup violation Fix: increase cycle time (can be done during chip operation) Short path: Hold time / functional violation Fix: insert buffers (can only be done at design time) ± Clock nonidealities (skew and jitter) (directly impact timing constraints) Impact of Clk skew on timing Impact of Clk jitter on timing D. Markovic / Slide 3 Lecture 11: Timing Analysis | 3 EEM216A .:. Fall 2010 R1 D Q Combinational Li In R2 D Q Timing (Cycle Time & Race Margin) Logic CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd D. Markovic / Slide 4 Cycle time: T Clk > t c q + t logic + t su Race margin: t hold < t c q,cd + t logic,cd Lecture 11: Timing Analysis | 4 EEM216A .:. Fall 2010
Clock Nonidealities ± Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK ± Clock jitter Tempora variations in consecutive edges of the clock signal; Clk Clk t SK JS D. Markovic / Slide 5 Temporal variations in consecutive edges of the clock signal; modulation + random noise ± Variation of the pulse width For level sensitive clocking Lecture 11: Timing Analysis | 5 EEM216A .:. Fall 2010 Clock Skew ± Distribution of clock tree insertion delay # of registers Earliest occurrence of Clk edge Nominal – T sk /2 Latest occurrence of Clk edge Nominal + T sk /2 D. Markovic / Slide 6 EEM216A .:. Fall 2010 Lecture 11: Timing Analysis | 6 Clk delay Insertion delay T skew Max Clk skew

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Sources of Skew and Jitter 4 Power Supply 2 3 Interconnect 5 Temperature 6 Capacitive Load 7 Coupling to Adjacent Lines 1 Clock Generation Devices D. Markovic / Slide 7 Lecture 11: Timing Analysis | 7 EEM216A .:. Fall 2010 Positive and Negative Skew CLK1 T CLK δ T CLK + 1 3 Positive: launching edge arrives before the receiving edge CLK2 + t h 2 4 T CLK T CLK + Negative: receiving edge arrives before the launching edge D. Markovic / Slide 8 Lecture 11: Timing Analysis | 8 EEM216A .:. Fall 2010 CLK1 CLK2 2 1 4 3
Signal Routing for Positive and Negative Skew R 1

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Lec-11_Timing-a - EE M216A Fall 2010 Lecture 11 Timing...

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