Lec-12_Clocking-a - EE M216A Fall 2010 Lecture 12 Clocking Issues Distribution Energy Prof Dejan Markovi ee216a@gmail.com Clock Distribution Goals

EE M216A .:. Fall 2010 Lecture 12 Clocking Issues: Distribution, Energy Prof. Dejan Markovi ć [email protected] Clock Distribution Goals: – Deliver clock to all memory elements with acceptable skew – Deliver clock edges with acceptable sharpness Clock network design is another one of the big challenges in the design of a large chip Clocks are generally distributed via wiring trees Want to use low ‐ resistance interconnect to minimize delay D. Markovic / Slide 2 Want to use low resistance interconnect to minimize delay Use multiple drivers to distribute driver requirements – Use optimal sizing principles to design buffers – Clock lines can create significant crosstalk EEM216A .:. Fall 2010 Lecture 12: Clocking Issues | 2

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Issues in Clock Distribution Network Skew – Process, voltage, temp. – Data dependence N i li Skew from Clk distribution – Noise coupling – Load balancing Power, CV 2 f – (no ½ or α ) – Clock gating Flexibility/Tunability – Compactness D. Markovic / Slide 3 ● fit into existing layout/design Reliability – Electromigration See videos from P. Restle (IBM) on classwiki EEM216A .:. Fall 2010 Lecture 12: Clocking Issues | 3 Clock Distribution Methods RC ‐ Tree – Less capacitance – More accuracy Fl ibl i i Grids − Reliable − Less data dependency T bl (l t i d i ) – Flexible wiring − Tunable (late in design) D. Markovic / Slide 4 Shown here for final stage drivers driving F ‐ F loads EEM216A .:. Fall 2010 Lecture 12: Clocking Issues | 4

RC Trees, Clock Distribution Observe: only relative skew is important H ‐ Tree X ‐ Tree Binary ‐ Tree D. Markovic / Slide 5 EEM216A .:. Fall 2010 CLOCK H-Tree Network Asymmetric trees that match RCs can be used Lecture 12: Clocking Issues | 5 More Realistic H ‐ Tree D. Markovic / Slide 6 EEM216A .:. Fall 2010 [Restle98] Lecture 12: Clocking Issues | 6

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The Grid System No RC ‐ matching Large power GCLK clock DEC Alpha Examples Driver Driver Driver GCLK GCLK grid 21064 21164 D. Markovic / Slide 7 EEM216A .:. Fall 2010 Driver GCLK 21264 Lecture 12: Clocking Issues | 7 Examples of Distribution H ‐ Tree Asymmetric RC ‐ Tree Grids DEC [Alphas] Serpentines Intel x86 [Young ISSCC97] – IBM D. Markovic / Slide 8 EEM216A .:. Fall 2010 Lecture 12: Clocking Issues | 8

Examples of Processor Chips DEC ‐ Alpha 21064 clock spines DEC ‐ Alpha 21064 RC delays Note: reverse Z ‐ axis DEC ‐ Alpha 21164 RC delays DEC ‐ Alpha 21164 RC local D. Markovic / Slide 9 EEM216A .:. Fall 2010 for global distribution Spine + Grid delays Lecture 12: Clocking Issues | 9 Example: EV5 (Alpha 21164) Clocking (1995) t rise = 0.35ns t skew = 150ps t cycle = 3.3ns Single phase clocking Clock Drivers Single ‐ phase clocking 2 distributed driver channels − Reduced RC delay/skew − Improved thermal distribution − 3.75 nF clock load − 58 cm final driver width D. Markovic / Slide 10 EEM216A .:. Fall 2010 Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation Lecture 12: Clocking Issues | 10

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t rise = 0.15ns t skew = 50ps t cycle = 1.67ns Example: EV6 (Alpha 21264) Clocking (1998) 600MHz, 0.35 µ m CMOS Multiple conditional buffered clocks – 2.8 nF clock load – 40 cm final driver width