Lec-13_Logic-Synthesis-a

Lec-13_Logic-Synthesis-a - EE M216A .:. Fall 2010 Lecture...

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Unformatted text preview: EE M216A .:. Fall 2010 Lecture 13 Logic Synthesis Prof. Dejan Markovi ee216a@gmail.com Design Challenges: An Industrial View TIMING AREA POWER DESIGNER RUNTIME MEMORY D. Markovic / Slide 2 Correct functionality requirements EEM216A .:. Fall 2010 Lecture 13: Logic Synthesis | 2 TIME TO MARKET Logic Synthesis Constraining your design for logic synthesis Design constraints Environmental constraints Driver Load (max fanout) Define clocks Cycle time Uncertainty Optimization constraints D. Markovic / Slide 3 Optimization constraints In and out delay / max transition Max area etc. (Timing exceptions) EEM216A .:. Fall 2010 Lecture 13: Logic Synthesis | 3 Logic Synthesis is Timing Driven This is a generic design used during synthesis Internal data path delay (cycle (and hold) time analysis) Relationship to in and out paths Ti i ti Timing exceptions D Q QB D Q QB FF 2 FF 3 TOP A Clk Z D. Markovic / Slide 4 EEM216A .:. Fall 2010 Lecture 13: Logic Synthesis | 4 Timing Constraints Clock period: set by define_clock Input delay: arrival of an external path with respect to a Clk edge Output delay: timing path from an output port to a register input of an external block of an external block D. Markovic / Slide 5 EEM216A .:. Fall 2010 Lecture 13: Logic Synthesis | 5 Input and output delays budget timing for surrounding logic in general case when the in/out ports are not registered Understanding Timing Constraints Three important constraints (clock, input, output) Blue box = current_design (to be retimed) logic logic logic logic logic Clk (input) (internal) (output) D. Markovic / Slide 6 set_input_delay (affects input logic) set_output_delay (affects output logic) create_clock (affects internal logic) EEM216A .:. Fall 2010 Lecture 13: Logic Synthesis | 6 Environment: Drivers, Load To simulate realistic inputs, we can set the driving cell using the external_driver command, to be any cell in the library This ensures that the input has a finite slew rate The load capacitance can be set on the output ports using the external_pin_cap command By default the Encounter RTL Compiler only tries to meet the timing constraints without optimizing power D. Markovic / Slide 7 If the max_dynamic_power attribute is set to some value, the tool tries to meet the timing specs while also optimizing for power in the process EEM216A .:. Fall 2010 Lecture 13: Logic Synthesis | 7 Example: Automated Adder Synthesis Copy the following files to your work directory /usr/public.2/ee216a/cadence/SOC62/SynLib.v /usr/public.2/ee216a/cadence/SOC62/adder.v / bli 2/ 216 / d /SOC62/ dd t /usr/public.2/ee216a/cadence/SOC62/adder.tcl The top level synthesis script adder.tcl reads in the HDL file, sets timing, load and power constraints, and runs synthesis To run RTL synthesis type the following command > rc files adder.tcl gui D. Markovic / Slide 8 The GUI window will show detailed architecture (gate level). Use The GUI window will show detailed architecture (gate level)....
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Lec-13_Logic-Synthesis-a - EE M216A .:. Fall 2010 Lecture...

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