Lec-14_Floorplanning-a

Lec-14_Floorplanning-a - EE M216A .:. Fall 2010 Lecture 14...

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EE M216A .:. Fall 2010 Lecture 14 Chip Floorplanning, Placement & Routing Prof. Dejan Markovi ć [email protected] Floorplanning: Overview Introduction: With ever larger designs, it is increasingly important to plan a design at an early stage. This early plan helps constrain later design decisions in terms of area, wire usage, ports, and port locations. The early stage plan, a.k.a. a floorplan , is fleshed out with increasing details with the design flow. The issue is a chicken and egg problem in that an accurate floorplan is difficult without knowing the details, and yet, building the details is greatly facilitated with a floorplan . So such a plan is a first guess. We use a lot of estimates for area to arrive at a reasonable plan. The plan discussed in this lecture includes area for blocks, ports and their locations routing channels metal layer usage power D. Markovic / Slide 2 and their locations, routing channels, metal layer usage, power and ground routing, clock routing, and I/O pins. The result is a diagram of the chip… Lecture 15: Floorplanning | 2 EEM216A .:. Fall 2010
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Design Flow: Floorplanning Floorplan D. Markovic / Slide 3 Lecture 15: Floorplanning | 3 EEM216A .:. Fall 2010 Floorplanning ± This is a plan of the chip, Shows the module/blocks The space needed for wires In a cell it is called the “color plan”; at the chip level “floorplan” ± How V DD , V GND , and Clock are distributed + wire width ± The area is estimated by the type of block (dpath or ctrl) ± The routing is based on position of I/O pins of each block Floorplanning tools will help position large blocks, rotating, flipping to minimize the routing between blocks Helps predict wiring loads and area of chip Makes sure you have enough pins, and space ± D. Markovic / Slide 4 Early in design Floorplan budgets area, wire area/delay. Negotiate tradeoffs ± Late in design Make sure the pieces fit together as planned Implement the global layout Lecture 15: Floorplanning | 4 EEM216A .:. Fall 2010
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Floorplanning ± Input Required Design netlist Area requirements Optional I/O placement Macro placement information Power requirements Timing constraints Physical partitioning information Die size vs. performance tradeoff ± Output (design ready for standard cell placement) Die/block area D. Markovic / Slide 5 I/Os placed Macros placed Power grid designed Power pre routing Standard cell placement areas Lecture 15: Floorplanning | 5 EEM216A .:. Fall 2010 Floorplanning Output I/O pads macro macro Std cells D. Markovic / Slide 6 Lecture 15: Floorplanning | 6 EEM216A .:. Fall 2010
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A Conceptual Floorplan ± Blocks inside a pad frame ± Routing may be inside blocks but need to blocks but need to interconnect them ± Brick and Mortar Random sized blocks that are more difficult than standard cell rows to route RAM std cell Blocks I/O pads Routing channel D. Markovic / Slide 7 ± Layout hierarchy not deep Tough to do this too many times data path channels Lecture 15: Floorplanning | 7 EEM216A .:. Fall 2010 Example Chip Layout D. Markovic / Slide 8 Lecture 15: Floorplanning | 8 EEM216A .:. Fall 2010
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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Lec-14_Floorplanning-a - EE M216A .:. Fall 2010 Lecture 14...

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