Lec-15_Multi-Vdd

Lec-15_Multi-Vdd - Multiple Voltage Domains (with Software...

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Multiple Voltage Domains (with Software Labs) Material from Vazgen Melikyan, Synopsys Co-developed for MSE Conference 2009 and Synopsys University Program 1 Prof. Dejan Markovi ć Electrical Engineering Department University of California, Los Angeles. Low Power Design Flow RTL Power Constructs RTL Simulation Definition of power domain Isolation behavior of a particular signal Retention behavior of particular registers Power domain simulation Isolation logic simulation Create Power Domains Logic Synthesis Physical Implementation Clock Gating Apply OpCond on blocks Special cell Insertion Retention Cell Synthesis Compile MV DFT Voltage Area Creation MTCMOS Insertion Physical synthesis Leakage optimization MCMM Scan reordering MV aware CTS Libraries 2 Verification Signoff MV aware Routing RTL vs. Gates matching Static Low Power Checks Parasitic Extraction SI, Timing, Power Signoff Power Network Analysis
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UPF 3 Unified Power Format (UPF) UPF UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process No existing HDL adequately supports the specification of power distribution and management Vendor-specific formats are non-portable and create 4 opportunities for bugs via inconsistent specifications
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UPF: Definition UPF Definition Define power distribution architecture Power domains Supply rails Create power management (operational) scenarios Switches Power state tables Set usage of special low power cells 5 Switches Isolation Level shifters Retention UPF: Basic Design Flow Design Specification (XML) RTL UPF + Power Aware RTL and Gate Level Functional Verification Like Simulation Pattern to Verify Logic Synthesis Gate Level UPF Physical Synthesis + • Power states from PST • Isolation value • Retention •… Formal and Structural Verification like Correct Implementation of 6 Gate Level PG Gate Level UPF + 1 Power Format for Implementation and Verification • Isolation • Level shifter • Switches
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Library Requirements for UPF (1) • Level shifters – Identified in .lib by is_level_shifter : true; • Isolation cells – Identified in .lib by • Retention registers – Identified in .lib by is_isolation_cell : true; retention_cell : cell_type; 7 • Power switch (MTCMOS) cells – Identified in .lib by switch_cell_type : coarse_grain; Library Requirements for UPF (2) • Power / ground (PG) pin definitions are required for all cells in a library – Defined as attributes in lib pg_pin(VDD) { std_cell_main_rail : true ; Defined as attributes in .lib – Allows accurate definition of multiple power / ground pin information • Benefits – Power domain driven synthesis – Automatic power net connections voltage_name : VDD; pg_type : primary_power; } pg_pin(VSS) { voltage_name : VSS; pg_type : primary_ground; } 8 – PST-based optimization – Verification of PG netlist vs.
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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Lec-15_Multi-Vdd - Multiple Voltage Domains (with Software...

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