Lec-04-Manufacturing

Lec-04-Manufacturing - EE115C Winter 2007 Digital...

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EE115C – Winter 2007 Digital Electronic Circuits Lecture 4: MOS Capacitance CMOS Manufacturing EE115C – Winter 2007 2 Announcements ± Starting next week: Wed (3-4pm) discussions Moved to MS-5118 ± Homework #1 posted Due Thu, Jan 25 @ 2pm ± Seminar next Monday, Jan 22 54-134 Eng IV, 1-2pm Extending and Expanding Moore's Law -- Challenges and Opportunities Shekhar Borkar Intel Microprocessor Technology Lab

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EE115C – Winter 2007 3 Agenda ± Last Lecture Subthreshold MOS IV characteristics Modes of Operation: Off, Linear, Velocity Saturation , Saturation MOS RC Model ± Today MOS Capacitances Delay Analysis EE115C – Winter 2007 4 MOS Transistor: Regions of Operation Linear Relationship -4 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 x 10 Velocity Saturation V DS (V) I D (A) V DS = V GT V DSAT = V GT Saturation Linear V DS = V DSAT ± Define V GT = V GS –V T V DSAT L · ξ c
EE115C – Winter 2007 5 B D G I D S () DS GT D V V V V L W k I + = λ 1 2 ' 2 min min for V GT 0: I D =0 with V min = min ( V GT , V DS , V DSAT ) for V GT 0: define V GT = V GS V T Regions of Operation: Simply look at the Min function… Sat Lin V-Sat A Unified Model for Manual Analysis EE115C – Winter 2007 6 Also Sub-Threshold Conduction… Typical values for S: 60 – 100 mV/decade The Slope Factor ox D nkT qV D C C n e I I GS + = 1 , ~ 0 S is V GS for I D 2 / I D 1 =10 0 0.5 1 1.5 2 2.5 10 -12 10 -10 10 -8 10 -6 10 -4 10 -2 V T Linear Exponential Quadratic V GS (V) I D (A) 0 11 GS DS qV qV nkT kT DD S II e e V  =− × +  

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EE115C – Winter 2007 7 B D G I D S () DS GT D V V V V L W k I + = λ 1 2 ' 2 min min for V GT 0 (sub-V TH ): with V min = min ( V GT , V DS , V DSAT ) for V GT 0 (Lin, Sat, V-Sat): define V GT = V GS V T Summary: Deep Submicron MOS I-V Model Sat Lin V-Sat 0 11 GS DS qV qV nkT kT DD S II e e V  =− × +   EE115C – Winter 2007 8 .MODEL Parameters MOS1 (Basic Parameters) ± .MODEL Modname NMOS/PMOS <VT0= VT0 …>