Lec-05-DesignRules-CMOS-Inverter

Lec-05-DesignRules-CMOS-Inverter - EE115C Winter 2007...

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EE115C – Winter 2007 Digital Electronic Circuits Lecture 5: Design Rules & Layout CMOS Inverter -- VTC EE115C – Winter 2007 2 Announcements ± Check the class web-page often Updates, announcements, handouts ± Reminder: Homework #1 due Thursday 2pm In class or Drop-off box: 56-125BB
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EE115C – Winter 2007 3 This Week: Design Metrics ± Cost of ICs ± Reliability ± Speed ± Power EE115C – Winter 2007 4 Cost of Integrated Circuits ± NRE (Non-Recurrent Engineering) costs – fixed design time and effort, mask generation independent of sales volume / number of products one-time cost factor indirect costs (the company overhead) R&D, manufacturing equipment etc. ± Recurrent costs – variable silicon processing, packaging, test proportional to volume proportional to chip area
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EE115C – Winter 2007 5 NRE Cost is Increasing EE115C – Winter 2007 6 Total Cost ± Cost per IC ± Variable cost volume cost fixed IC per cost variable IC per cost + = yield test final packaging of cost test die of cost die of cost cost variable + + =
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EE115C – Winter 2007 7 Die Cost Single die Wafer Going up to 12” (30cm) yield die * per wafer dies wafer of cost die of cost = From: http://www.amd.com EE115C – Winter 2007 8 Yield % 100 per wafer chips of number Total per wafer chips good of Number × = Y yield Die per wafer Dies cost Wafer cost Die × = ( ) area die 2 diameter wafer area die diameter/2 wafer per wafer Dies 2 × × π × π =
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EE115C – Winter 2007 9 Defects α α × + = area die area unit per defects 1 yield die α≈ 3, complexity of mfg. process defects per unit area = 0.5 to 1 /cm 2 cost of die = f (die area) 4 EE115C – Winter 2007 10 Some Examples (1994) $417 9% 40 296 1.5 $1500 0.80 3 Pentium $272 13% 48 256 1.6 $1700 0.70 3 Super Sparc $149 19% 53 234 1.2 $1500 0.70 3 DEC Alpha $73 27% 66 196 1.0 $1300 0.80 3 HP PA 7100 $53 28% 115 121 1.3 $1700 0.80 4 Power PC 601 $12 54% 181 81 1.0 $1200 0.80 3 486 DX2 $4 71% 360 43 1.0 $900 0.90 2 386DX Die cost Yield Dies/w afer Area mm 2 Def./ cm 2 Wafer cost Line width Metal layers Chip yield Die per wafer Dies cost Wafer cost Die × =
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EE115C – Winter 2007 11 Cost per Transistor 0.0000001 0.000001 0.00001 0.00001 0.0001 0.001 0.001 0.01 0.01 0.1 0.1 1 1982 1985 1988 1988 1991 1994 1994 1997 2000 2000 2003 2003 2006 2009 2009 2012 cost: cost: ¢-per per -transistor transistor Fabrication capital cost per transistor (Moore’s law) Today: ~10,000 transistors/¢ (~100n$ / transistor)
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Lec-05-DesignRules-CMOS-Inverter - EE115C Winter 2007...

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