Lec-07-Delay-Wires

# Lec-07-Delay-Wires - EE115C Winter 2007 Digital Electronic...

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EE115C – Winter 2007 Digital Electronic Circuits Lecture 7: Propagation Delay Introduction to Wires EE115C – Winter 2007 2 Announcements ± Midterm in two weeks Tuesday, Feb 13 ± TA’s office hours (proposal) Time: Wednesday 1-2pm (instead of Friday 11am-12pm) Location: 67-112 Engr IV

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Design Metrics Propagation Delay EE115C – Winter 2007 4 V out t f t pHL t pLH t r t V in t 90% 10% 50% 50% 2 pHL pLH p t t t + = Performance: Delay Definitions
EE115C – Winter 2007 5 v 0 v 1 v 5 v 1 v 2 v 0 v 3 v 4 v 5 T = 2 × t p × N Technology Characterization: Ring Oscillator for t p Tutorial 2: t p = 13ps EE115C – Winter 2007 6 Performance: FO4 Inverter ± Measures quality of design across different technology generations d Tutorial 2: FO4 = 33ps

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EE115C – Winter 2007 7 V out I avg V DD V in = V DD C L avg swing L pHL I V C t 2 = DD n L pHL V k C t ~ CMOS Inverter Propagation Delay: Approach 1 MOS Current Model EE115C – Winter 2007 8 A First-Order RC Network v out v in C R Important model – matches delay of inverter in t out v e t v = ) 1 ( ) ( τ Step response: RC t p 69 . 0 2 ln = = Propagation delay: Delay: 0.69 RC 90% point: 2.2 RC
EE115C – Winter 2007 9 V out R n V DD V in = V DD C L ) ( L on pHL C R f t = L on C R = 69 . 0 0.36 0.5 1 R on C L t V out ln(0.5) V DD CMOS Inverter Propagation Delay: Approach 2 MOS Resistance Model EE115C – Winter 2007 10 Review: Transistor as a Switch V GS V T SD R on () + + + = 2 1 2 1 2 1 DD DSAT DD DD DSAT DD eq V I V V I V R λ DD DSAT DD eq V I V R 6 5 1 4 3 I D V DS V DD V DD /2 V GS = V DD R mid R 0 0 2 1 R R R mid eq + = Traversed path

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## This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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Lec-07-Delay-Wires - EE115C Winter 2007 Digital Electronic...

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