M216A_1_Lec-08-Leakage-Power-n2

M216A_1_Lec-08-Leakage-Power-n2 - EEM216A Fall 2008 Lecture...

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Low Power Design: Leakage Power EEM216A – Fall 2008 Lecture 8 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 ± Dynamic Power Reduction (Cont.) Multiple supply voltages Dynamic voltage scaling Clock gating, datapath activity reduction ± Standby Power Reduction Longer channels Stack effect / complex gates Multiple thresholds Sleep transistors Variable threshold CMOS Today
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EEM216A / Fall 2008 D. Markovic / Slide 3 + Variable V T Sleep T’s Multi-V DD Variable V T + Input control Stack effects + Multi-V T Leakage DFS, DVS Clock Gating Logic design Scaled V DD TSizing Multi-V DD Active Run Time Sleep Mode Design Time Energy Variable Throughput/Latency Constant Throughput/Latency Power/Energy Optimization Space EEM216A / Fall 2008 D. Markovic / Slide 4 Year 2002 ’04 ’06 ’08 ’10 ’12 ’14 ’16 0 0.2 0.4 0.6 0.8 1 1.2 0 20 40 60 80 100 120 Technology node[nm] Voltage [V] V TH V DD Technology node 2002 ’04 ’06 ’08 ’10 ’12 ’14 ’16 0 1 2 Year P DYNAMIC P LEAK Power [μW / gate] Subthreshold leak (Active leakage) T. Sakurai, ISSCC 03 The Leakage Challenge
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EEM216A / Fall 2008 D. Markovic / Slide 5 Source: S. Borkar, Intel The Leakage Challenge (Cont.) 130nm 30% 5X Frequency ~30% ~30% Leakage Leakage Power Power ~5 -10X 10X 0.9 1.0 1.0 1.1 1.2 1.3 1.3 1.4 1 2 3 4 5 Normalized Leakage ( Normalized Leakage ( Isb Isb ) Normalized Frequency EEM216A / Fall 2008 D. Markovic / Slide 6 10 -2 10 -1 10 0 10 1 0 0.2 0.4 0.6 0.8 1 E Leakage /E Switching E Op / nominal E re f nominal parallel pipeline V th ref -180mV 0.81V dd max V th ref -95mV 0.57V dd V th ref -140mV 0.52V dd Optimal designs have high leakage (E Lk /E Sw 0.5) Must adapt to process variations and activity Flip Side: Leakage is Good for You!
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EEM216A / Fall 2008 D. Markovic / Slide 7 ± Design time techniques Transistor-level multi-V TH design Stack Effect Gate level/Synthesis approaches ± Standby/runtime leakage control MTCMOS/ power-down Substrate bias (VTCMOS) Self-substrate bias (SSB) Self-adjusting threshold voltage (SAT) Standby power reduction (SPR) SAT+SPR Working with Leakage EEM216A / Fall 2008 D. Markovic / Slide 8 ± Using higher thresholds Channel doping Body biasing Stacked devices ± Using longer transistors Limited benefit Increase in active current ± Reducing the voltage!!
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M216A_1_Lec-08-Leakage-Power-n2 - EEM216A Fall 2008 Lecture...

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