M216A_1_Lec-09-ED-Optimization-n2

M216A_1_Lec-09-ED-Optimization-n2 - EEM216A Fall 2008...

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Energy-Delay Optimization EEM216A – Fall 2008 Lecture 9 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 ± Friday, Nov 7 2:00 pm – 4:00 pm Location: TBD ± Material included All lectures up to (including) next Monday ± Midterm review In-class, Wed, Nov 5 ± Open book/notes ± Infrastructure update (new space you can use) /w/class/dejan/ee216a/project_f2008/<ee_user> Midterm: Next Week
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EEM216A / Fall 2008 D. Markovic / Slide 3 ± Homeworks Hw 2 solutions online / grading in progress Hw 3 coming up today Hw 4 will include a project task EEM216A Roadmap Class project Launch Final report Phase 1 1 Wk 2 3 4 5 6 7 8 9 10 h1 h2 h3 h4 M 10/10 10/24 11/5 11/19 11/7 P 12/5 Today EEM216A / Fall 2008 D. Markovic / Slide 4 Today ± Energy-delay optimization ± Some common questions Is sizing better than V DD for energy reduction? What are the optimal values of gate size and V DD ? What is the optimal ratio of leakage / switching for min E? Shall we increase or decrease V DD for energy reduction? What is the optimal circuit topology? How many levels of parallelism is good? Etc.
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EEM216A / Fall 2008 D. Markovic / Slide 5 Delay Unoptimized design var 1 var 2 var 1 & var 2 all vars Energy E max D max D min E min (f clk max ) (f clk min ) Achieve the lowest Energy under the Delay constraint Energy Minimization Problem EEM216A / Fall 2008 D. Markovic / Slide 6 [D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, JSSC, Aug’04] Energy-Delay Sensitivity E/ A D/ A A=A 0 S A = S B S A f(A 0 ,B) f(A,B 0 ) Delay Energy D 0 (A 0 ,B 0 )
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EEM216A / Fall 2008 D. Markovic / Slide 7 Solution: Equal Sensitivities E = S A · ( D)+ S B · D At the solution point all sensitivities should be equal f(A 0 ,B) f(A,B 0 ) Delay Energy D 0 (A 0 ,B 0 ) D 1 ,B) EEM216A / Fall 2008 D. Markovic / Slide 8 topology A topology B Delay Energy/op Constraints Circuit Optimization Goal: find optimal E-D tradeoff for a logic function ± Reference design D min sizing @ V dd max , V th ref
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EEM216A / Fall 2008 D. Markovic / Slide 9 0.5 0.6 0.7 0.8 0.9 1 0 0.5 1 1.5 2 2.5 3 3.5 4 V dd / V dd ref FO4 delay (norm.) V on = 0.37 V α d = 1.53 simulation model Combined with Logical Effort Formulation (*) (*) [Sutherland et al., Logical Effort, 1999] (90nm technology) V dd ref = 1.2V, FO4 (V dd ref ) = 25ps Alpha-power based Delay Model ± Fitting parameters V on , α d , K d ± Effective fanout . EEM216A / Fall 2008 D. Markovic / Slide 10 with: D : the cycle time I 0 ( S in ): normalized leakage current with inputs in state S in ± Switching energy ± Leakage energy Energy Model Includes term
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EEM216A / Fall 2008 D. Markovic / Slide 11 ± Delay ± Leakage energy Including Threshold Control: V TH ± Impacts delay and leakage energy ± V th can be from body bias or different V th device EEM216A / Fall 2008 D. Markovic / Slide 12 i i+1 W wire p nom,i W i W i , dd i V ,1 dd i V + W i+1 W i W par,i W out Sizing Supply = energy stored on the logic gate i More About Switching Component of Energy
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EEM216A / Fall 2008 D. Markovic / Slide 13 ± Reference/nominal circuit – sized for D min @ V dd nom ± Define delay constraint –D con =D min (1+d inc /100) ±
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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M216A_1_Lec-09-ED-Optimization-n2 - EEM216A Fall 2008...

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