M216A_1_Lec-10-Adders-n2

M216A_1_Lec-10-Adders-n2 - EEM216A Fall 2008 Lecture 10...

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Adders EEM216A – Fall 2008 Lecture 10 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 ± Basic terminology ± Adder building blocks ± Basic adder topologies Linear adders (n < 16) Fast parallel adders (n > 16) ± Some examples Today: Adders
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EEM216A / Fall 2008 D. Markovic / Slide 3 Loopback bus Adder core Adder core Sum 2:1 Mux External operands Shift control 5:1 Mux 6:1 Mux Mux control O/p Mux Mux control External operands Sign control Courtesy: R. Krishnamurthy (Intel) 32-Bit ALU Architecture Multiple ALUs clustered together in the execution core High power density EEM216A / Fall 2008 D. Markovic / Slide 4 Execution core Cache Integer and FP ALUs and MACs Temp ( o C) Courtesy: R. Krishnamurthy (Intel) Processor thermal map ± ALUs: performance and peak-current limiters ± Goal: high-performance energy-efficient design ALUs are Thermal Hotspots
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EEM216A / Fall 2008 D. Markovic / Slide 5 A Brief Look at Numbers ± The number of bits determines the “width” of the datapath ± Fixed point numbers Integer Unsigned 0 to 2 N -1 Signed -2 N-1 to 2 N-1 -1 2’s complement representation (complement + 1) ± Floating point numbers Mantissa + Exponent = N bits 2.14 (mantissa) x10 4(exponent) 64 bits, 54 bits mantissa, 10 bits exponent EEM216A / Fall 2008 D. Markovic / Slide 6 Simple Addition ± Grade school addition 0110011 +0010001 --------- 1000100 ± Use an adder cell per bit position ± Half adder A+B = Sum, Carry_out ± Full adder A+B+Carry_in = Sum, Carry_out a.k.a 3-2 adder Half adder Full adder
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EEM216A / Fall 2008 D. Markovic / Slide 7 Full Adder: Logic Implementation ± Function within a 3-2 Adder ± Sum function S o =1 when Odd input 1’s S o = XOR(A,B,C i ) S o = A x B x C i ± Carry function C o =1 when 2 or more input 1’s C o = Majority(A,B,C i ) C o = AB + BC i + AC i 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 C o S o C i B A Full adder Sum C out C in AB SA B C i ⊕⊕ = A =B C i ABC i i +++ C o BC i AC i ++ = Binary Adder EEM216A / Fall 2008 D. Markovic / Slide 8 Basic Architecture: Ripple-Carry Adder ± Sum is calculated starting at LSB Carry “ripples” from LSB into higher order bits to compute the sums and generate the next carry ± Max delay t delay = t sum + (N-1) t carry Half Adder Full Adder A 0 B 0 S 0 C 1 A 1 B 1 S 1 C 2 Full Adder A n-1 B n-1 S n-1 C n C n-1
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EEM216A / Fall 2008 D. Markovic / Slide 9 AB B A C i C i A X V DD V DD A B C i B A B V DD A B C i C i A B A C i B C o V DD S Complementary Static CMOS Full Adder 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 C o S o C i B A 28 Transistors = C o ± Implement as separate gates… Not as efficient (especially XOR) ± Generate carry first (longer critical path) Use carry to generate sum EEM216A / Fall 2008 D. Markovic / Slide 10 Layout Considerations ± Design each adder so that they can easily stack Embed wiring into design ± Use a single cell Can’t share V DD and V GND ± 2 bits per slice to share supply rails Mirror the cells A 0 B 0 A 1 B 1 S 0 S 1 C 0 A 0 B 0 A 1 B 1 S 0 S 1 C 0 C 1 C 2 Stacked bit-slices Mirrored bit-slices A 2 B 2 S 0 C 3 Dual slice C 1 C 2
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EEM216A / Fall 2008 D. Markovic
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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M216A_1_Lec-10-Adders-n2 - EEM216A Fall 2008 Lecture 10...

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