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M216A_1_Lec-13-Timing-n2

# M216A_1_Lec-13-Timing-n2 - EEM216A Fall 2008 Lecture 13...

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Timing EEM216A – Fall 2008 Lecture 13 Dejan Markovic [email protected] EEM216A / Fall 2008 D. Markovic / Slide 2 Homeworks Hw #2 will be graded by Tue night Hw #3 solutions, online by Tue noon Hw #4 posted online (due Fri, Nov 21) Lectures this week Due to holiday on Tue, video of Mon lec will be available on Wed Wed lecture: Logic synthesis (by Sourabh Tandon / Synopsys Inc.) Office hours this week Monday: 4:30pm – 6:00pm (business as usual) Wed: no office hours (out of town / ICCAD) Wed OH moves to Friday 4:00pm – 5:30pm Announcements

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EEM216A / Fall 2008 D. Markovic / Slide 3 Today Midterm Avg = 60% Std.dev = 13% Max = 90% / Min = 30% Class project Description online Team sign-up: classwiki Timing analysis How to make flip-flops Delay and power analysis How to do timing analysis Datapath logic + F/F’s 10 20 30 40 50 60 70 80 90 100 0 5 10 15 percentage score number of students EEM216A, Fall 2008, Midterm Total scores µ = 60.6 % σ = 13.4 % max = 90.0 % min = 30.0 % (36 students) 0-50 scale EEM216A / Fall 2008 D. Markovic / Slide 4 Two Types of Machines with State (Storage) Two quite different abstract models: Data storage used for computation ( Data Flows ) In this abstraction, the storage is used to hold data that is being manipulated. In this model the number of bits of state can be enormous, but it does not matter. It is simply the data-set that is being manipulated. State is not that important, it is the flow of data that is critical. States for sequencing information ( Finite State Machines ) In this abstraction, the storage is used to hold your place in some decision making process. It indicates where you are, and using this information you decide what to do next. The amount of state (number of unique decision points) is finite, and usually limited. One could think about drawing out the ‘decision graph’ showing the possible transitions between states.
EEM216A / Fall 2008 D. Markovic / Slide 5 Brief Introduction to Clocking Means to synchronize By allowing events to happen at known timing boundaries, we can sequence these events Greatly eases building of FSMs Clock strobe indicates the moment when states are stored No need to worry about variable delay through the CL All signals are delayed until the clock edge (clock imposes the worst case delay) register register register Dataflow FSM Comb Logic Comb Logic EEM216A / Fall 2008 D. Markovic / Slide 6 V i1 V o2 V o2 = V i1 V o1 = V i2 V i1 A C B V o2 V i1 = V o2 Positive Feedback: Bi-Stability State storage…

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EEM216A / Fall 2008 D. Markovic / Slide 7 Gain should be larger than 1 in the transition region A C d B V i2 5 V o1 V i1 5 V o2 A C d B V i2 5 V o1 V i1 5 V o2 Meta-Stability EEM216A / Fall 2008 D. Markovic / Slide 8 Cross-Coupled Pairs Forbidden State S S R Q Q Q Q R S Q Q 0 0 Q 1 0 1 0 0 1 0 1 0 1 1 0 R Q NOR-based set-reset The “Overpowering” Approach
EEM216A / Fall 2008 D. Markovic / Slide 9 Writing into a Static Latch CLK CLK CLK D Q D CLK CLK D Converting into a MUX Forcing the state Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states EEM216A / Fall 2008 D. Markovic / Slide 10 Storage Mechanisms D CLK CLK Q Dynamic CLK CLK CLK D Q Static

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M216A_1_Lec-13-Timing-n2 - EEM216A Fall 2008 Lecture 13...

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