M216A_1_Lec-14-Logic-Synthesis-n2

M216A_1_Lec-14-Logic - EEM216A Fall 2008 Lecture 14 Logic Synthesis Sourabh Tandon Dejan Markovic [email protected] [email protected]

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Logic Synthesis EEM216A – Fall 2008 Lecture 14 Dejan Markovic [email protected] Sourabh Tandon [email protected] Substituting for EEM216A / Fall 2008 D. Markovic / Slide 2 Design Challenges DESIGNER CORRECT FUNCTIONALITY REQUIREMENTS TIMING AREA POWER RUNTIME MEMORY TIME TO MARKET
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EEM216A / Fall 2008 D. Markovic / Slide 3 High-Level Design Issues ± You may think design is a straightforward logical process Start with the idea of what you need to build And then build it ± Real design is not like that Think you have an idea of what you need to build Through the design process you figure out what you really want to build Need to validate basic idea early in the process ± What you build depends on the implementation capabilities and constraints Implementation issues will change the specification Need a language that helps with the real (interactive) design process Specification Implementation Verification EEM216A / Fall 2008 D. Markovic / Slide 4 Hardware Description Languages ± Need a description level up from logic gates ± Work at the level of functional blocks, not logic gates Complexity of the functional blocks is up to the designer A functional unit could be an ALU, or could be a microprocessor ± The description consists of functional blocks and their interconnections Describe functional block (not predefined) Support hierarchical description (function block nesting) ± To make sure the specification is correct, make it “executable” Run the functional specification and check what it does
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EEM216A / Fall 2008 D. Markovic / Slide 5 Hardware Description Languages ± A hardware description language (HDL) translates the specification of a hardware device into a software medium; This software medium can be Verified via simulation Translated into an optimized, technology-specific, gate- level implementation ± Register Transfer Level (RTL) synthesis explicitly defines register boundaries and the combinational logic between them: Data flow, control flow, and machine states are explicitly defined by the coding style that is used EEM216A / Fall 2008 D. Markovic / Slide 6 Hardware Description Languages (Examples) ± There are many different systems for modeling and simulating hardware Verilog VHDL L-language, M-language (Mentor) DECSIM (DEC) Aida (IBM / HaL) and many others ± The two most standard languages: Verilog & VHDL For this class we will be using Verilog Given to UCLA for classes Have both a simulator and synthesis tools that work with Verilog IEEE Standard
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EEM216A / Fall 2008 D. Markovic / Slide 7 Verilog from 20,000 Feet ± Verilog descriptions look like programs: ± Block structure is a key principle Use hierarchy/modularity to manage complexity ± But they aren’t ‘normal’ programs Module evaluation is concurrent Model is really that of communicating blocks C / Pascal Verilog Procedures/Functions Procedure parameters Variables Modules Ports Wires / Regs EEM216A / Fall 2008 D. Markovic / Slide 8 Verilog (or any HDL) View of the World ±
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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M216A_1_Lec-14-Logic - EEM216A Fall 2008 Lecture 14 Logic Synthesis Sourabh Tandon Dejan Markovic [email protected] [email protected]

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