M216A_1_Lec-15-Timing-Synthesis-n2

# M216A_1_Lec-15-Timing-Synthesis-n2 - EEM216A Fall 2008...

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Timing Analysis (Cont.), Logic Synthesis: A Practical View EEM216A – Fall 2008 Lecture 15 Dejan Markovic [email protected] EEM216A / Fall 2008 D. Markovic / Slide 2 Timing Analysis ± Basic timing constraints Long paths (cycle time / setup violations) Short paths (hold time / hold violations) ± Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing ± Flip-flop vs. latch timing Time borrowing (latches only)

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EEM216A / Fall 2008 D. Markovic / Slide 3 Timing Analysis (1): Cycle Time (Long Path) ± Determines minimum cycle time (maximum speed) May affect performance, do not affect functionality ± Cycle time constraint (setup time) T cycle = T Clk-Q + T Logic,max + T setup + T skew (to be explained later) D Q Clk D Q Clk Logic N t Logic T Clk-Q t Setup T cycle EEM216A / Fall 2008 D. Markovic / Slide 4 Timing Analysis (2): Hold Time (Short Path) ± Min-delay paths could cause race conditions Irreparable post-silicon (unless you FIB the chip) ± Min-delay constraint (hold time) T hold < T Logic,min + T Clk-Q Clk t Clk-Q t logic,min Clk t hold
EEM216A / Fall 2008 D. Markovic / Slide 5 R1 DQ Combinational Logic In CLK t CLK1 R2 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Cycle time: T Clk > t Clk-Q + t logic,max + t su Race margin: t hold < t Clk-Q + t logic,min Timing (Cycle Time & Race Margin) EEM216A / Fall 2008 D. Markovic / Slide 6 Setup and Hold Times ± Defined with respect to closing clock edge Both in latches and flip-flops (built from latches) ± Could be positive or negative Implementation dependent Setup time Master-Slave CSEs have positive setup Pulse-trigered CSEs have negative setup Hold time Master-Slave CSEs may have close-to-zero or negative hold time Pulse-triggered CSEs have large positive hold time

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EEM216A / Fall 2008 D. Markovic / Slide 7 Positive Setup Time t Clk t D t Q DATA STABLE DATA STABLE Register Clk DQ t setup t hold t Clk-Q EEM216A / Fall 2008 D. Markovic / Slide 8 Negative Setup Time t Clk t D t Q DATA STABLE DATA STABLE Register Clk t setup t hold t Clk-Q Race hazard
EEM216A / Fall 2008 D. Markovic / Slide 9 • Transparent to D only when Clk and Clk 1 are both high • Limited clock uncertainty absorption • Data can arrive after the clock (negative setup time) • But large positive hold time / race hazard D Q Clk S Clk 1 HLFF: Example of Negative Setup Time Partovi et al. 1996 EEM216A / Fall 2008 D. Markovic / Slide 10 Clock Nonidealities ± Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK ± Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL ± Variation of the pulse width for level-sensitive clocking

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EEM216A / Fall 2008 D. Markovic / Slide 11 Clock Skew and Jitter ± Both skew and jitter affect the effective cycle time ± Only skew affects the race margin Clk Clk t SK t JS EEM216A / Fall 2008 D. Markovic / Slide 12 Clock Skew # of registers Clk delay Insertion delay Earliest occurrence of Clk edge Nominal – T sk /2 Latest occurrence of Clk edge Nominal + T sk /2 T skew Max Clk skew
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## This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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M216A_1_Lec-15-Timing-Synthesis-n2 - EEM216A Fall 2008...

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