M216A_1_Lec-16-Clocking-n2

M216A_1_Lec-16-Clocking-n2 - EEM216A Fall 2008 Lecture 16...

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Clocking Methodologies EEM216A – Fall 2008 Lecture 16 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 Clock Distribution ± Goals: Deliver clock to all memory elements with acceptable skew Deliver clock edges with acceptable sharpness ± Clock network design is another one of the big challenges in the design of a large chip ± Clocks are generally distributed via wiring trees ± Want to use low-resistance interconnect to minimize delay ± Use multiple drivers to distribute driver requirements Use optimal sizing principles to design buffers Clock lines can create significant crosstalk
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EEM216A / Fall 2008 D. Markovic / Slide 3 Issues in Clock Distribution Network ± Skew Process, voltage, temp. Data dependence Noise coupling Load balancing ± Power, CV 2 f – (no ½ or α ) Clock gating ± Flexibility/Tunability Compactness fit into existing layout/design ± Reliability Electromigration See videos from P. Restle (IBM) on classwiki Skew from Clk distribution EEM216A / Fall 2008 D. Markovic / Slide 4 Clock Distribution Methods ± RC-Tree Less capacitance More accuracy Flexible wiring ± Grids Reliable Less data dependency Tunable (late in design) Shown here for final stage drivers driving F-F loads
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EEM216A / Fall 2008 D. Markovic / Slide 5 CLOCK H-Tree Network RC Trees, Clock Distribution Observe: Only relative skew is important H-Tree X-Tree Binary-Tree Asymmetric trees that match RCs can be used EEM216A / Fall 2008 D. Markovic / Slide 6 More Realistic H-Tree [Restle98]
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EEM216A / Fall 2008 D. Markovic / Slide 7 The Grid System Driver Driver Driver GCLK GCLK GCLK GCLK ± No RC-matching ± Large power clock grid DEC Alpha Examples 21064 21164 21264 EEM216A / Fall 2008 D. Markovic / Slide 8 Examples of Distribution H-Tree Asymmetric RC-Tree IBM Grids DEC [Alphas] Serpentines Intel x86 [Young ISSCC97]
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EEM216A / Fall 2008 D. Markovic / Slide 9 Examples of Processor Chips DEC-Alpha 21064 clock spines DEC-Alpha 21064 RC delays DEC-Alpha 21164 RC delays for global distribution Spine + Grid DEC-Alpha 21164 RC local delays Note: reverse Z-axis EEM216A / Fall 2008 D. Markovic / Slide 10 Clock Drivers Example: EV5 (Alpha 21164) Clocking (1995) t rise = 0.35ns t skew = 150ps t cycle = 3.3ns ± Single-phase clocking ± 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75 nF clock load 58 cm final driver width ± Local inverters for latching ± Conditional clocks in caches to reduce power ± More complex race checking ± Device variation 9.3M Transistors P Clock = 20 W (total 50 W)
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EEM216A / Fall 2008 D. Markovic / Slide 11 ± Multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width ± Reduced load/skew ± Reduced thermal issues ± Multiple clocks complicate race checking t rise = 0.15ns t skew = 50ps t cycle = 1.67ns Global clock waveform PLL Example: EV6 (Alpha 21264) Clocking (1998) 600MHz, 0.35 µ m CMOS EEM216A / Fall 2008 D. Markovic / Slide 12 21264 Clocking
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EEM216A / Fall 2008 D. Markovic / Slide 13 GCLK Skew (at Vdd/2 Crossings) ps 5 10 15 20 25 30 35 40 45 50 ps 300 305 310 315 320 325 330 335 340 345 GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%)
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M216A_1_Lec-16-Clocking-n2 - EEM216A Fall 2008 Lecture 16...

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