M216A_1_Lec-17-Floorplanning-n2

M216A_1_Lec-17-Floorplanning-n2 - EEM216A Fall 2008 Lecture...

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Floorplanning, Placement & Routing EEM216A – Fall 2008 Lecture 17 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 Announcements / Agenda ± Project Plug-and-play testbench released Instructions available on classwiki Phase 1: electronic submission ( ee216a@gmail.com ) Writeup (1 page) Choice of circuit topology Optimization strategy Block-level performance and power ± Homework #4 solutions online ± Today’s lecture Floorplanning, placement & routing
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EEM216A / Fall 2008 D. Markovic / Slide 3 Project: “Official” ALU Test Circuit ± Setup instructions on classwiki (copy lib cells and testvectors) ± All you need to do is place your ALU inside “alu” cell and maintain pin naming convention , go back to “test_alu” and push “simulate” button to obtain Energy and delay numbers I(V DD ) V DD,ctrl Clk EEM216A / Fall 2008 D. Markovic / Slide 4 Drivers… ± Parasitic cap of final driver is accounted for, together with input gate cap of the ALU
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EEM216A / Fall 2008 D. Markovic / Slide 5 Load… ± Load of 16x (n = 16) ± C out for Miller EEM216A / Fall 2008 D. Markovic / Slide 6 Floorplanning: Overview Introduction: With ever larger designs, it is increasingly important to plan a design at an early stage. This early plan helps constrain later design decisions in terms of area, wire usage, ports, and port locations. The early stage plan, a.k.a. a floorplan , is fleshed out with increasing details with the design flow. The issue is a chicken-and-egg problem in that an accurate floorplan is difficult without knowing the details, and yet, building the details is greatly facilitated with a floorplan . So such a plan is a first guess. We use a lot of estimates for area to arrive at a reasonable plan. The plan discussed in this lecture includes area for blocks, ports and their locations, routing channels, metal layer usage, power and ground routing, clock routing, and I/O pins. The result is a diagram of the chip…
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EEM216A / Fall 2008 D. Markovic / Slide 7 Design Flow: Floorplanning Floorplan EEM216A / Fall 2008 D. Markovic / Slide 8 Floorplanning ± This is a plan of the chip, Shows the module/blocks The space needed for wires In a cell it is called the “color plan”; at the chip level - “floorplan” ± How V DD , V GND , and Clock are distributed + wire width ± The area is estimated by the type of block (dpath or ctrl) ± The routing is based on position of I/O pins of each block Floorplanning tools will help position large blocks, rotating, flipping to minimize the routing between blocks Helps predict wiring loads and area of chip Makes sure you have enough pins, and space ± Early in design Floorplan budgets area, wire area/delay. Negotiate tradeoffs ± Late in design Make sure the pieces fit together as planned Implement the global layout
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EEM216A / Fall 2008 D. Markovic / Slide 9 Floorplanning ± Input Required Design netlist Area requirements Power requirements Timing constraints Physical partitioning information Die size vs. performance tradeoff ±
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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M216A_1_Lec-17-Floorplanning-n2 - EEM216A Fall 2008 Lecture...

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