M216A_1_Lec-18-Power-Distribution-n2

M216A_1_Lec-18-Power-Distribution-n2 - EEM216A Fall 2008...

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Power Distribution EEM216A – Fall 2008 Lecture 18 Dejan Markovic [email protected] EEM216A / Fall 2008 D. Markovic / Slide 2 Power = … Routing resources 20-40% of all metal tracks used by Vdd, Gnd Increased power Æ denser power grid Pins Vdd or Gnd pin carries 0.5-1W of power Pentium 4 uses 423 pins: 233 Vdd or Gnd More pins Æ higher cost package (+ package development, board design…) Battery cost 1kg NiCd can power P4 for <1hr Performance High chip temperature degrades performance Large across-chip temp variations induce clk skew High chip power limits use of high-perf cicruits Power transients determine min supply Courtesy: A. Kahng
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EEM216A / Fall 2008 D. Markovic / Slide 3 Power = Package Courtesy: A. Kahng EEM216A / Fall 2008 D. Markovic / Slide 4 Packaging Package functions Mechanical connection of chip to board Electrical connection of signals and power from chip to board with very little delay or distortion Short wires with low R and L Removes heat produced on chip and thermal expansion and stress Protects chip from mechanical damage Inexpensive to manufacture and test Main issues: Cost Thermal impedance: how effectively package removes heat from the die Lead inductance Ceramic pin grid array package – lowest [Reading: Weste, Harris VLSI book]
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EEM216A / Fall 2008 D. Markovic / Slide 5 Package Types Through-hole vs. surface mount EEM216A / Fall 2008 D. Markovic / Slide 6 Multi-Chip Modules Pentium Pro MCM Fast connection of CPU to cache Expensive, requires known good dice
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EEM216A / Fall 2008 D. Markovic / Slide 7 Concept of a Typical Chip Package Chip Mounting Cavity Lead Frame Bonding Wire Pin L L’ EEM216A / Fall 2008 D. Markovic / Slide 8 Traditionally, chip is surrounded by pad frame Metal pads on 100 – 200 µ m pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling Chip-to-package Connections
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EEM216A / Fall 2008 D. Markovic / Slide 9 Chip / Package Alignment Alight top-left corners and do simple bonding Top Left (index marker) die package Top Left (L-shapes) EEM216A / Fall 2008 D. Markovic / Slide 10 Example Package Data Sheet SSM P/N CPG12028 www.spectrum semi.com
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EEM216A / Fall 2008 D. Markovic / Slide 11 Figure out Pin Locations (PCB Routing) 120 pins chip: 3.5mm 2 Ceramic PGA SSM P/N CPG12028 (~ $30) Test socket YAMAICHI NP89-19601 -KS11730 (~ $70) 90 87 86 83 81 78 77 74 71 69 66 63 61 93 92 89 85 82 79 75 73 70 67 65 62 57 96 95 91 88 84 80 76 72 68 64 60 59 56 99 97 94 101 100 98 104 103 102 107 105 106 108 109 110 111 112 114 113 115 118 116 119 1 117 2 5 120 3 6 58 55 53 54 52 51 50 49 48 46 45 47 42 43 44 38 40 41 34 37 39 31 35 36 29 32 33 26 27 30 4 8 12 16 20 24 28 7 10 13 15 19 22 25 9 11 14 17 18 21 23 A B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 EEM216A / Fall 2008 D. Markovic / Slide 12 Advanced Packages Bond wires contribute parasitic inductance Fancy packages have many signal, power layers Like tiny printed circuit boards Flip-chip places connections across surface of die rather than around periphery Top level metal pads covered with solder balls Chip flips upside down Carefully aligned to package (done blind!)
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