M216A_1_Lec-19-Memory-n2

M216A_1_Lec-19-Memory-n2 - EEM216A Fall 2008 Lecture 19...

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Memory EEM216A – Fall 2008 Lecture 19 Dejan Markovic [email protected] EEM216A / Fall 2008 D. Markovic / Slide 2 Semiconductor Memory ± It is an important component 30% of the worldwide semiconductor business DRAMs are a very high volume product Embedded all non-memory parts as well ± Often drives technology development Technologies can be specialized for memory DRAM have special capacitors, SRAMs special loads ± Intense “device-level” circuit design process Large benefit to improved circuit performance Digital and analog design issues ± A good reference application for the material in this course! More details about memory: EE215B
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EEM216A / Fall 2008 D. Markovic / Slide 3 Types of Memory ± There are many types of memory Usually distinguished by type of memory and access method ± Access methods Random access memory – RAM You can access any memory location at the same speed Most common type of memory Content address memory – CAM Access memory by a search on its contents E.g. find location where the upper byte is 250 ± Memory Types Static – SRAM, read/write memory Dynamic – DRAM, read/write/refresh memory Read only – ROM, read mostly (PROM, EEPROM) Programmable ROM, Electrically Erasable PROM EEM216A / Fall 2008 D. Markovic / Slide 4 Random Access Chip Architecture ± Think about a linear array of addresses that store data Each box holds some data But this does not lead to a nice layout shape Too long and skinny ± Create a 2-D array Decode Row and Column address to get data
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EEM216A / Fall 2008 D. Markovic / Slide 5 Memory Organization EEM216A / Fall 2008 D. Markovic / Slide 6 Basic Memory Array CORE : - keep square within a 2:1 ratio - rows are word lines - columns are bit lines DECODERS : - needed to reduce total number of pins; N+M address lines for 2 N+M bits of storage Ex: if N+M=20 2 20 = 1Mb MULTIPLEXING : - used to select one or more columns for input or output of data - data in and out on columns DATA r ow de co der col-decoder/mux Cell Array 2 N x 2 M 1 . . . N M ... “CORE” 1 1 2 N 1 2 M
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EEM216A / Fall 2008 D. Markovic / Slide 7 Memory Timing: Definitions EEM216A / Fall 2008 D. Markovic / Slide 8 Static Memory Cell ± Uses only six transistors (called 6T cell): ± Read and write operations use the same port. There is one wordline and two bit lines. The bit lines carry complementary data. The cell layout is small since it has a small number of wires. Wordline Bit Bit_b
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EEM216A / Fall 2008 D. Markovic / Slide 9 WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q 6-Transistor CMOS SRAM Cell EEM216A / Fall 2008 D. Markovic / Slide 10 WL BL V DD M 5 M 6 M 4 M 1 V DD V DD V DD BL Q = 1 Q = 0 C bit C bit CMOS SRAM Analysis (Read)
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EEM216A / Fall 2008 D. Markovic / Slide 11 CMOS SRAM Analysis (Read) 0 0 0.2 0.4 0.6 0.8 1 1.2 0.5 11.2 1.5 2 Cell Ratio (CR) 2.5 3 Voltage Rise (V) EEM216A / Fall 2008 D. Markovic / Slide 12 BL = 1 BL = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V DD WL CMOS SRAM Analysis (Write)
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EEM216A / Fall 2008 D. Markovic / Slide 13 CMOS SRAM Analysis (Write) EEM216A / Fall 2008 D. Markovic / Slide 14 V DD GND Q Q WL BL BL M1 M3 M4 M2 M5 M6 WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q 6T-SRAM Layout
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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M216A_1_Lec-19-Memory-n2 - EEM216A Fall 2008 Lecture 19...

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