M216A_1_Lec-20-Testability-n2

M216A_1_Lec-20-Testability-n2 - EEM216A Fall 2008 Lecture...

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Testability EEM216A – Fall 2008 Lecture 20 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 Admin Info: Project / Final ± Final project report (more info on classwiki) Final report (up to 6 pages), due: Fri, Dec 5 (2pm) Email: ee216a@gmail.com ± Office hours during the finals week Mon, Dec 8, 2:00-4:00pm (56-147E Eng-IV) ± Final exam Wednesday, Dec 10, 11:30am – 2:30pm Closed book, you may bring two-page notes
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EEM216A / Fall 2008 D. Markovic / Slide 3 Overview Reading W&H: Chapter 9 Introduction – ± Silicon debugging is a growing problem that accompanies the increasing complexity of current designs. This lecture discusses how chips fail, how chips are tested and debugged. ± Design for Test and Debug” is the art of adding functionality to the chip to enhance its controllability and observability so that it can be effectively debugged and tested for correct operation. Controllability: the ability to set the state of internal nodes from the chip’s input pads. Observability: the ability to propagate the state of internal nodes to the chip’s output pads. Most slides in this lecture are from: Shannon Morton, (SGI), ISSCC 2003 EEM216A / Fall 2008 D. Markovic / Slide 4 Do you want unhappy customers? ± Pentium FP divider bug in 1994 cost the company $450 million dollars. People got fired over this! Yo Dude ! Where do you want this truck load of returns !! Express Returns
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EEM216A / Fall 2008 D. Markovic / Slide 5 Technology Scaling ± IC Scaling: 0.7x technology shrink 2x increase in number of internal nodes From 1 µ m technology to 0.1 µ m 100x increase in complexity of internal state Die size also increasing even more states Only a small relative increase in the number of pins available for test. Longer lengths of interconnect (over a mile!) More layers & tighter pitches more IC faults ± Complexity A combinational logic with N inputs implies 2 N test vectors. A sequential logic with N inputs and M states implies 2 N+M test vectors. EEM216A / Fall 2008 D. Markovic / Slide 6 ± Man-hours required to generate sufficient test coverage (if at all possible) is vastly increased. ± Testing occurs at different stages and costs differently Wafer, packaged chip, board, system, field 10x more expensive at each level (wafer probing is $0.1/unit) ± Each part requires more time/tester, or more testers 50M units at 1sec/unit $5 million/year. At least $2-3 million for a 1000-pin tester. Reduced volume unable to meet demand loss of potential revenue ± Increased risk of shipping defective parts Unhappy customers loss of ongoing revenue Cost of Testing
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EEM216A / Fall 2008 D. Markovic / Slide 7 Why Chips Fail? ± Process defects ± Reliability failures ± Iddq failures ± Timing and noise failures ± Soft errors ± Logic design failures EEM216A / Fall 2008 D. Markovic / Slide 8 Process Defect Examples ± Missing or poorly formed via ( infant mortality ) ± Hillock causing an open in upper layer metal SEM Courtesy of IBM [4] SEM Courtesy of Accurel [5] ± Random and systematic defects
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This note was uploaded on 10/19/2011 for the course ELECTRICLA 216A taught by Professor Marković during the Fall '10 term at UCLA.

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M216A_1_Lec-20-Testability-n2 - EEM216A Fall 2008 Lecture...

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