04_pipeline

04_pipeline - This Unit: (Scalar In-Order) Pipelining App...

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CIS 501 (Martin): Pipelining 1 CIS 501 Computer Architecture Unit 4: Pipelining Slides originally developed by Amir Roth with contributions by Milo Martin at University of Pennsylvania with sources that included University of Wisconsin slides by Mark Hill, Guri Sohi, Jim Smith, and David Wood. CIS 501 (Martin): Pipelining 2 This Unit: (Scalar In-Order) Pipelining • Principles of pipelining • Effects of overhead and hazards • Pipeline diagrams • Data hazards • Stalling and bypassing • Control hazards • Branch prediction • Predication CPU Mem I/O System software App App App Readings • Chapter 2.1 of MA:FSPTCM CIS 501 (Martin): Pipelining 3 Datapath Background CIS 501 (Martin): Pipelining 4
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CIS 501 (Martin): Pipelining 5 Recall: The Sequential Model • Basic structure of all modern ISAs • Processor logically executes loop at left Program order : total order on dynamic insns • Order and named storage define computation • Convenient feature: program counter (PC) Insn itself at memory[PC] • Next PC is PC++ unless insn says otherwise Atomic : insn X finishes before insn X+1 starts • Can break this constraint physically (pipelining) • But must maintain illusion to preserve programmer sanity Fetch PC Decode Read Inputs Execute Write Output Next PC CIS 501 (Martin): Pipelining 6 Datapath and Control Datapath : implements execute portion of fetch/exec. loop Functional units (ALUs), registers, memory interface Control : implements decode portion of fetch/execute loop Mux selectors, write enable signals regulate flow of data in datapath Part of decode involves translating insn opcode into control signals PC I$ Register File s1 s2 d D$ + 4 control CIS 501 (Martin): Pipelining 7 Single-Cycle Datapath Single-cycle datapath : true “atomic” fetch/execute loop Fetch, decode, execute one complete instruction every cycle “Hardwired control” : opcode to control signals ROM + Low CPI: 1 by definition Long clock period: to accommodate slowest instruction PC I$ Register File s1 s2 d D$ + 4 CIS 501 (Martin): Pipelining 8 Multi-Cycle Datapath Multi-cycle datapath : attacks slow clock Fetch, decode, execute one complete insn over multiple cycles Micro-coded control : “stages” control signals Allows insns to take different number of cycles (main point) ± Opposite of single-cycle: short clock period, high CPI (think: CISC) PC I$ Register File s1 s2 d D$ + 4 D O B A
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CIS 501 (Martin): Pipelining 9 Single-cycle vs. Multi-cycle Performance • Single-cycle • Clock period = 50ns, CPI = 1 • Performance = 50ns/insn • Multi-cycle has opposite performance split of single-cycle + Shorter clock period – Higher CPI • Multi-cycle • Branch: 20% ( 3 cycles), load: 20% ( 5 cycles), ALU: 60% ( 4 cycles) • Clock period = 11ns , CPI = (20%*3)+(20%*5)+(60%*4) = 4 • Why is clock period 11ns and not 10ns? • Performance =
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04_pipeline - This Unit: (Scalar In-Order) Pipelining App...

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