final08

final08 - 1 Prof. Martin Wednesday, Dec. 10, 2008 CIS501...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 Prof. Martin Wednesday, Dec. 10, 2008 CIS501 Computer Architecture Final Exam This exam is an individual-work exam. Write your answers on these pages. Additional pages may be attached (with staple) if necessary. Please ensure that your answers are concise and legible. Read and follow the directions of each question carefully. Please attempt to answer all the questions (dont allow yourself to get stuck on a single question). You have 120 minutes to complete the exam (approximately one point per minute). If you are taking this exam as a WPE-I: Your WPE-I Number: If you are NOT taking this exam as a WPE-I: Name: Problem Page Possible Score 1 2 10 2 3 5 3 4 6 4 5 9 5 6 6 6 7 8 7 8 8 8 9 11 9 10 8 10 12 8 11 13 11 Total 90 2 1. [ 10 Points ] True or False . If a statement is false, briefly explain how so by describing how the statement may most simply be made true. Unjustified (or poorly justified) false answers will be marked wrong. Simply stating the negation of the false statement is not sufficient justification. Please be specific! (a) Power-related issues are relevant only when designing battery-powered devices. (b) Smaller transistors generally use less energy when switching. (c) Reliability is an increasing concern as transistors continue to shrink in size. (d) For a cache of a fixed capacity, doubling the associativity of the cache will halve the size of the tag array. (e) A victim buffer improves the average miss penalty of a cache. (f) A write buffer (also called a store buffer) is primarily intended to hide store latency. (g) Assuming similar pipeline depths, improving branch prediction accuracy is generally more im- portant in a superscalar (multiple-issue) processor than in a scalar (single-issue) processor. (h) Because branch prediction is so critical for performance, a processor today typically uses a branch predictor that is 1 MB or larger. (i) A branch target buffer (BTB) is tagged because it must be correct; in contrast, a branch direction predictor is untagged because it is only a predictor and thus does not always need to be correct. (j) When a cache block in the E cache coherence state is evicted from the cache, it must be written back to the memory. 3 2. [ 5 Points ] (a) Processor Performance . Assume a typical program has the following instruction type break- down: 35% loads 10% stores 50% adds 3% multiplies 2% divides Assume the current-generation processor has the following instruction latencies: loads: 4 cycles stores: 4 cycles adds: 2 cycles multiplies: 16 cycles divides: 50 cycles If for the next-generation design you could pick one type of instruction to make twice as fast (half the latency), which instruction type would you pick? Why?...
View Full Document

Page1 / 13

final08 - 1 Prof. Martin Wednesday, Dec. 10, 2008 CIS501...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online