final08-solutions

final08-solutions - 1 Prof. Martin Wednesday, Dec. 10, 2008...

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Unformatted text preview: 1 Prof. Martin Wednesday, Dec. 10, 2008 CIS501 Computer Architecture Final Exam Solutions 1. [ 10 Points ] True or False . If a statement is false, briefly explain how so by describing how the statement may most simply be made true. Unjustified (or poorly justified) false answers will be marked wrong. Simply stating the negation of the false statement is not sufficient justification. Please be specific! (a) Power-related issues are relevant only when designing battery-powered devices. Answer: False, cooling issues limit the power dissipation (and thus the performance) of server and desktop processors. (b) Smaller transistors generally use less energy when switching. Answer: True. (c) Reliability is an increasing concern as transistors continue to shrink in size. Answer: True. (d) For a cache of a fixed capacity, doubling the associativity of the cache will halve the size of the tag array. Answer: False. Associativity doesnt change the overall number of frames in the cache, and thus doesnt change the number or size of the tags significantly. (e) A victim buffer improves the average miss penalty of a cache. Answer: True. (f) A write buffer (also called a store buffer) is primarily intended to hide store latency. Answer: True. (g) Assuming similar pipeline depths, improving branch prediction accuracy is generally more im- portant in a superscalar (multiple-issue) processor than in a scalar (single-issue) processor. Answer: True. (h) Because branch prediction is so critical for performance, a processor today typically uses a branch predictor that is 1 MB or larger. Answer: False, branch predictors are in the low kilobytes of state, not a thousand kilobytes. (i) A branch target buffer (BTB) is tagged because it must be correct; in contrast, a branch direction predictor is untagged because it is only a predictor and thus does not always need to be correct. Answer: False, both the BTB or direction predictor are just predictors, and thus neither needs to be correct. (j) When a cache block in the E cache coherence state is evicted from the cache, it must be written back to the memory. Answer: False, the E is a clean state, so it isnt written back. When a block in the M state is evicted, it is dirty and must update the memory. 2. [ 5 Points ] 2 (a) Processor Performance . Assume a typical program has the following instruction type break- down: 35% loads 10% stores 50% adds 3% multiplies 2% divides Assume the current-generation processor has the following instruction latencies: loads: 4 cycles stores: 4 cycles adds: 2 cycles multiplies: 16 cycles divides: 50 cycles If for the next-generation design you could pick one type of instruction to make twice as fast (half the latency), which instruction type would you pick? Why?...
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This note was uploaded on 10/19/2011 for the course CS 501 taught by Professor Matin during the Fall '10 term at UPenn.

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final08-solutions - 1 Prof. Martin Wednesday, Dec. 10, 2008...

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