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Final09 - 1 Prof Martin Tuesday Dec 22 2009 CIS501– Computer Architecture Final Exam This exam is an individual-work exam Write your answers on

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Unformatted text preview: 1 Prof. Martin Tuesday, Dec. 22, 2009 CIS501– Computer Architecture Final Exam This exam is an individual-work exam. Write your answers on these pages. Additional pages may be attached (with staple) if necessary. Please ensure that your answers are concise and legible. Read and follow the directions of each question carefully. Please attempt to answer all the questions (don’t allow yourself to get stuck on a single question). You have 120 minutes to complete the exam (approximately one point per minute). If you are taking this exam as a WPE-I: Your WPE-I Number: If you are NOT taking this exam as a WPE-I: Name: Problem Page Possible Score 1 2 7 2 3 8 3 4 11 4 5 9 5 6 9 6 7 10 7 8 10 8 10 15 9 11 9 10 12 8 11 13 14 Total 110 2 1. [ 7 Points ] True or False . If a statement is “false,” briefly explain how so by describing how the statement may most simply be made true. Unjustified (or poorly justified) “false” answers will be marked wrong. Simply stating the negation of the false statement is not sufficient justification. Please be specific! (a) “The Alpha 21264 architecture is very dynamic.” (b) Moore’s law predicts an exponential improvement in transistor switching speeds over time. (c) The cost to manufacture a chip is proportional to the area of the chip. (d) A compiler optimization can increase performance yet hurt CPI. (e) Clustering (such as that used by the Alpha 21264) is one approach for tackling the n 2 problem of dependence cross checking logic. (f) Assuming similar pipeline depths, high branch prediction accuracy is generally more important in a superscalar (multiple-issue) processor than in a scalar (single-issue) processor. (g) An easy way to exploit data parallelism in your programs is to call library code that has been optimized to use vector instructions. 3 2. [ 8 Points ] Multiplying Performance . (a) Consider a computation that consists of calculating the sum of thousands of integers. Using a simple single-cycle datapath as a starting point, what are four techniques or approaches we discussed that each can increase performance by a factor of four or more (that is, altogether these four techniques could result in a 256x speedup!) (Single word answers are sufficient.) 1. 2. 3. 4. 4 3. [ 11 Points ] Performance & ISAs (Part 2) . An alternative way of accelerating the computation from the previous question is introducing a new three-input ADD3 instruction to your favorite ISA. This new instruction operates on normal 64-bit registers only and performs the computation A = B + C + D . (a) What impact– if any –would adding the ADD3 instruction have on the following aspects of a pipelined datapath: Instruction fetch: Stall logic: Bypassing: Register file: Execution units: Data cache: (b) What impact– if any –would adding this ADD3 instruction have on the following aspects of a dynamically-scheduled pipeline?...
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This note was uploaded on 10/19/2011 for the course CS 501 taught by Professor Matin during the Fall '10 term at UPenn.

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Final09 - 1 Prof Martin Tuesday Dec 22 2009 CIS501– Computer Architecture Final Exam This exam is an individual-work exam Write your answers on

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