chap2-090908v6 - CHAPTER 2 The Microprocessor and CHAPTER...

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Unformatted text preview: CHAPTER 2 The Microprocessor and CHAPTER its Architecture Contents of this chapter: Contents of this chapter: • 1. Describe the function and purpose of each program­visible register. • 2. Detail the flag register and the purpose of each flag bit. • 3. Real mode memory­addressing techniques. • 4. Protected mode memory­addressing techniques. • 5. Describe the program­invisible registers. • 6. Memory­paging mechanism. 2.1 INTERNAL MICROPROCESSOR ARCHITECTURE 2.1 INTERNAL MICROPROCESSOR ARCHITECTURE 2.1.1 The Programming Model • general­purpose or multipurpose registers: – EAX, EBX, ECX, EDX, EBP, EDI, and ESI. – They hold various data sizes (bytes, words, or double words). • ADD AL,BL • ADD AX, CX • ADD EAX, ESI • Special­purpose Registers: – EIP, ESP, EFLAGS; – segment registers: CS, DS, ES, SS, FS, and GS. 2.1 INTERNAL MICROPROCESSOR ARCHITECTURE 2.1.1 The Programming Model 2.1.1 • C (carry) 1001 1000 1000 1000 • P (parity) +1111 0100 +0111 1000 • A (auxiliary carry) 1 1 0 0 0 1 1 0 0 10000 0000 • Z (zero) C=1,Z=0,A=0, C=1,Z=1,A=1 • S (sign) P=0, S=1, P=1,S=0 and FLAG register FIGURE 2­2 The EFLAG and FLAG register FIGURE 2­2 The EFLAG and FLAG register • T (trap) 1001 1000 0101 1000 • I (interrupt) +1111 0100 +0111 0100 • D (direction) 11000 1100 01100 1100 • O (overflow) OF=0 SF=1 OF=1 SF=1 – used for signed numbers, not for unsigned numbers. • IOPL (I/O privilege level), 00--highest, 11--Lowest level • NT (nested task) and FLAG register FIGURE 2­2 The EFLAG and FLAG register FIGURE 2­2 The EFLAG and FLAG register 2.2 REAL MODE MEMORY ADDRESSING 2.2 REAL MODE MEMORY ADDRESSING • The 80286 and above microprocessors operate in – the real mode­­­­ used in DOS – protected mode­­­­ used in Windows 95/98/2000/XP/2003, Linux, Sco Unix; • virtual 8086 mode: DOS process in windows 95/98/2000/XP. • general protected mode • 8086/8088 works only in real mode. • In real mode, total accessable memory size is 1 M bytes. 2.2.1 Segments And Offsets • e.g. MOV AX, [DI]; AX<­­ [1F000h] • segment DS=1000H, offset DI=F000H 1000 + F000 11.6 16550 ,,,,,,, • smart , • ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, 11.6.1 异异异异异异 ,,,,,,,,,, • ,,, 11.47, ,,,,,,,,,, 7 ,,,,,,,,,,,,,,,,,,, , ,,,,,,,,,, • ,,,,,,,,,,,,,,,,,,,,,, . • ,,,,,,,,,,,,,,,, . 2.2.2 Default Segment and offset Register 2.2.2 Default Segment and offset Register • e.g. mov [DI], 30B7H; add [EBP], EAX • program example: .model large ; multiple segments .stack 100H ; 100H bytes stack .data i dw 3 j dw 5 k dw ? .code ; 40byte .startup mov ax,i add ax,j mov k,ax .exit end • FIGURE 2­5 An application program containing a code, data, and stack segment loaded into a DOS system memory. – code: 1000H bytes – data: 190H bytes – stack: 200H bytes 2.3 Introduction To Protected Mode Memory 2.3 Introduction To Protected Mode Memory Addressing • Protected mode memory addressing (80286 and above) – allows access to data and programs exceeding 1M byte of memory. • see Fig 2­9: 16­bit segment register (selector) ­­­­> descriptor table ­­­­> 32­bit segment base address (in descriptor) • e.g. ADD AX, [EDI] – DS ­­>32­bit data segment base addr: 20001000H – suppose EDI=33334444H – linear addr=20001000+33334444H=53335444H – suppose paging is not enable, then linear address is just physical address. – physical address=53335444H – AX <­­ [53335444H] In protected mode, 32­bit linear address= 32­bit segment base address + 32­bit offset 2.3.1 Selector And Descriptor 2.3.1 Selector And Descriptor • 16­bit segment register = selector • It selects one of 8192 descriptors in one of two tables: – global descriptor table – local descriptor table: be unique to an application • Each descriptor table contains 8192 descriptors; • One descriptor describes one memory segment; • So a total of 16,384 segments are available to a application. • descriptor in a 80386 and above contains following fields: – 32­bit base address: locates the segment base address; – 20­bit limit: is the offset address of the last byte (or 4K block) in the segment; • e.g. a segment locates in 00f0 0000H­­00f0 00ffH, then the base address is 00f0 0000H, the limit is 000ffH; • the segment size is 100H byte. – access right , G, D, AV • G: granularity bit, – G=1, segment size=(limit+1)*4096 bytes – G=0, segment size=(limit+1) bytes • ,,,,,,, 00001 ,,,,,,,,,,, 1000 0000H ,, – , G , 1 ,,,,, 1000 0000H ,,,, 1000 1FFFH ,,,, 2000H=2*4K=8KB ,,, – , G , 0 ,,,,, 1000000H ,,,, 10000001H ,,,, 2 ,,, • D bit: indicates how the CPU instructions access register and memory data. – D=1: 32­bit instruction mode. all offset address and all registers are 32 bits by default. – D=0: 16­bit instruction mode. all offset address and all registers are 16 bits by default. • AV=1: the segment is available (in physical memory). – AV=0: the segment is not available (in disk, i.e. virtual memory). • The access rights byte controls access to the protected mode memory segment. – P=0: this descriptor is undefined, i.e. a free descriptor. – P=1: this descriptor is defined, it is used. – DPL: indicates this segment’s data privilege level (a kind of data attribute); DPL value: 00,01,10,11. • GDT (Global Descriptor Table) • LDT (Local Descriptor Table) • Difference between global descriptor and local descriptor: – global descriptor contains segment definitions that apply to all program. – local descriptor are usually unique to an application. • In protected mode, linear address=32­bit segment base address + 32­bit offset • Protected mode memory addressing (80286 and above) – allows access to data and programs exceeding 1M byte of memory. • Fig 2­8: segment register (CS,DS,SS,...) structure. • RPL: Requested Privilege Level, indicates the user’s privilege. – its values: 00,01,10,11. 00­­the highest. – if RPL of a user program matches or is higher than the DPL of the memory segment, access is granted; – e.g. RPL=01, DPL=02, then access is granted. – otherwise, the access is refused. ,,,, 0010 0000H 3# ,,, 000FFH 2# 异异异异异 异异 异异异异 异异异 异异异 异异异异异 异异 异异 异异 DS=0008H , 0000 0000 0000 1000 异异异 100H 异异 1# 0# 2.3.2 Program­Invisible registers 2.3.2 Program­Invisible registers • When a segment register changes its value, – e.g. MOV DS,AX ; MOV ES, AX ; RET – segment register (selector) selects a descriptor in the descriptor table; – Descriptor cache in program­invisible registers is loaded with the base address, limit, and access right of descriptor; • GDTR : Global Descriptor Table Register, it contains – theGDT’s base address (start address), the GDT’s limit. • IDTR : Interrupt Descriptor Table Register, it contains – the IDT’s base address (start address), the IDT’s limit. • LDTR : Local Descriptor Table Register. – it contains a selector; – the selector accesses the GDT and get base address, limit, access right; – CPU then store base address, limit, access right into descriptor cache. 2.3.2 Program­Invisible registers 2.3.2 Program­Invisible registers selector • Protected mode memory addressing (80286 and above) 32 bit 20 bit 8 bit – allows access to data and programs exceeding 1M byte of memory. selector point to LDT base address point to GDT base address 32 bit 16 bit point to IDT base address .data x dd 11223344H y dd 17a32c34H z dd 23H w dd ? .code mov ax, @data ; mov ax, 0240H mov ds, ax mov eax , x ; mov eax, [00000000H] add eax, y ; add eax, [00000004H] sub eax, z ; sub eax, [00000008H] mov w, eax ; mov [0000000cH], eax ...... 2.4 MEMORY PAGING 2.4 MEMORY PAGING segment reg. (selector) 32­bit offset addr. segment reg. (selector) 32­bit segment base addr. + 32­bit physical addr. (a) memory paging is disabled 32­bit segment base addr. + 32­bit linear addr. 32­bit offset addr. 32­bit physical addr. (b) memory paging is enabled Paging unit 2.4.1 Paging Register 2.4.1 Paging Register • CR0 (in next page) contains many control bits. – PG , Paging Enable , • if PG=1, the linear address is converted to a physical address through paging mechanism. • otherwise, linear address = physical address – PE , Protection Enable. • Set PE to 1 to select protected mode; • Clear this bit to make CPU to reenter real mode. • CR4 exists only in Pentium and above • CR0 contains many control bits. 异异异异 – ET , Processor Extension Type , MP , 1 ,,,,,,,,,,,,,,,, Processor Extension Type MP , • , ET , 0 ,,,, 80287 ,,,,,,, • , ET , 1 ,,,, 80387 ,,,,,,, – TS , Task Switched, ,, 80386 ,,,,,,, – EM , Emulate coprocessor, ,,,,,,,,, ESC ,,,, 7 ,,, (ESCape ,,,, 80387 ,,,,,,, ) ,,,,,, 7 ,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,, 100 ,, – MP , Monitor Processor , MP , 1 ,,,,,,,,,,,, (a) The format for the linear address (b) a page directory or page table entry 2.4.2 The Page Directory and Page Table 2.4.2 The Page Directory and Page Table • In a system based on 80386 or above , there is: – one page directory table. The table contains entries (<= 1024). • each entry is indexed by 10­bit DIR part of linear address; • each entry contains 20­bit base address of page table . – A maximal 1024 page tables. A table contains 1024 entry. • each entry is indexed by 10­bit Page part of linear address; • each entry contains 20­bit base address of a page. • each entry corresponds to a page; • each entry’s 20 bit base address plus 12­bit offset part of linear address constructs a 32­bit physical address. • 1024 page­table * 1024 entry /page­table * 4K byte / page­table­entry = 4 G bytes linear address structure 10bi t 10bi t 12bi t 32­bit linear address 异 异异异异异异异异异异 bit 异异异异 10bi t entry 20bi t 12bi t 10bi t 20 异异异异异异 20bi 30bi t 20 异异异异异 异 12t异 0 30bi t 20 异异异异异 entry 20 异异异异异 异 12 异 0 32­bit physical address • In the 80486 CPU, a cache called TLB is integrated. • TLB holds 32 translation address of the most recently accessed pages. • If the upper 12 bit of linear address is already present in the TLB, the access to page directory table and page table is not required. Upper 20­bit of linear address Upper 20­bit of physical address 1# 2# 3# .... 32# TLB , Translation look­aside buffer , , ,,,,,,, 异异异异异异异异异异异异异异异异 In Figure 2­14: • The first entry of page directory table is 00003003H; – This entry points to a page table 0# starts in address 00003000H; • One entry of page table is 00000003H; – This entry points to a page starts in address 00000000H; • Another entry of page table is 00110003H; – This entry points to a page starts in address 00110000H; – This page’s new physical address is 00110000­­ 00110FFFH; • Its old physical address is 000C8000­­000C8FFFH; Figure 2­14. The page directory,page table 0, and two memory pages 2.3 Introduction To Protected Mode Memory 2.3 Introduction To Protected Mode Memory • Addressing 000C8FFFH Protected mode memory addressing (80286 and above) (old) Page – allows access to data and programs exceeding 1M byte of table 0# memory. 4K byte 000C8000H , old , 4K byte Page directory table ...
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