chap5-091012v4 - CHAPTER 5 Arithmetic and Logic...

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Unformatted text preview: CHAPTER 5 Arithmetic and Logic Instructions CHAPTER Arithmetic • Among arithmetic and logic instructions, following instructions don't exist: – Both operands are memory data, e.g. ADD [BX], [SI] – One operand is a segment register, e.g. ADD AX, DS • Arithmetic and logic instructions affect OF, SF, ZF, AF, PF and CF, – except that the INC instruction don't affect CF. • After the execution of a instruction, – The flag is not affected, its value don’t change; – The flag is not defined, its value is not sure. 5.1 Addition, Subtraction, and Comparison 5.1 Addition, Subtraction, and Comparison 5.1.1 Addition • format: ADD REG/MEM, REG/MEM/IMM – REG: any 8­, 16­, or 32­bit multipurpose register ( and SP/ESP ( – MEM: operand in memory – IMM: immediate • operation: ADD Dest, Src – Dest <­­ Dest + Src • e.g. ADD CL, [BP]; ADD [EAX*4+ECX+20], BX; ADD ECX,EDX • Error: ADD MEM,MEM; ADD REG/MEM, SegReg – e.g. ADD [BX], [SI]; ADD AX, DS; ADD SS, AX • e.g. MOV word ptr [ECX+EDX*4+20H], 1234H – scaled­index: EDX*4 – 1­byte displacement: 20H – 2­byte immediate: 1234H • After arithmetic and logic instruction execution, only OF, SF, ZF, AF, PF and CF changes; – IF, TF and other flags don't change. – e.g. MOV DL, 12H ADD DL, 33H; Z=0,C=0,A=0,S=0,P=0,O=0 • E.g. ... array db 10,11,12,13,14,15,16,17 .... mov al, 0 mov si, 3 add al, array[si] add al, array[si+2] add al, array[si+4]; al=13+15+17 Increment Addition Increment Addition • INC REG/MEM • e.g. INC BL; INC word ptr [ESI*4+ECX]; INC ESP • Error: INC SegReg; e.g. INC DS • Note: the INC instruction affects OF, SF, ZF, AF, PF, but does not affect CF. Addition­with­Carry Addition­with­Carry • ADC DST ( SRC ( – DST ← DST +SRC +CF • Format: ADC REG/MEM, REG/MEM/IMM EXAMPLE 5­7 5.1.2 Subtraction 5.1.2 Subtraction • SUB DST ( SRC ( DST ← DST ( SRC DST • Format: SUB REG/MEM, REG/MEM/IMM • CF=1 and AF=1 if there is borrow • OF: indicate the signed number's overflow. – If the result of P+P, P­N is N, then OF=1. • i.e. For 8­bit number, the result>+127. e.g. 4AH+62H=ACH­­> ­54H • (here P: Positive number, N: negative number) – If the result of N+N, N­P is P, then OF=1 • i.e. For 8­bit number, the result<­128. e.g. B6H+9EH ­­> 54H, (or ­4AH+(­62H)=­ACH ­­­>+54H) – Otherwise, OF=0. • CF: – for addition, it indicates the overflow of two unsigned number's sum . • i.e. For 8­bit number, the sum>255. • e.g. C2H+62H=124H, CF=1, overflow – For subtraction, it indicates the borrow ( (( ) of two unsigned number's difference. • e.g. 32H­42H=50­66=­16=F0H, CF=1, there is borrow. • (((( CF ( 1 ((((( CF ( 0 ( – e.g. A4H­22H=82H, CF=0 22H­A4H=­82H, CF=1 Decrement Subtraction • DEC OPR ( OPR ← OPR ( 1 OPR • Format: DEC REG/MEM • E.g. DEC numb; DEC EBP; DEC DWORD PTR ES:[ECX+6] DEC ES:[ECX+6] ; Incorrect! Subtraction­with­borrow Subtraction­with­borrow • SBB DST ( SRC ( DST ← DST ( SRC ( CF DST CF • Format: SBB REG/MEM, REG/MEM/IMM • E.g. SBB EAX, [EBP*4] SBB CL, 2 ; CL <­­ CL­2­CF • E.g. EDX:EAX <­­ EDX:EAX ­ EBX:ECX – SUB EAX, ECX EDX EAX ­ EBX ECX – SUBB EDX, EBX Comparison • CMP OPR1 ( OPR2 ( OPR1 ( OPR2 OPR1 • Format: CMP REG/MEM, REG/MEM/IMM • CMP (((((((((((((((((((((((((((( Comparison and Exchange (80486 and above only) Comparison and Exchange • CMPXCHG DST ( SRC ( (((((((((((( AL ( AX ( EAX ( – If AX=DST – then ZF ← 1 ( DST ← SRC DST – Else ZF ← 0 ( AX ← DST AX CMPXCHG8B ((((( 8 (((( (((( • CMPXCHG8B DST ( DST ( 8 ((((( DST – If EDX:EAX = DST – then ZF ← 1 ( (DST) ← (ECX ( EBX) (DST) (← (DST) – else ZF ← 0 (( EDX ( EAX (← (DST) 5.2 Multiplication and Division 5.2 Multiplication and Division 5.2.1. Multiplication • MUL SRC ­­­­ unsigned integer's multiplication. • Format: MUL REG/MEM • Operation: MUL SRC – SRC is byte operand ( AX ← AL × SRC AX – SRC is word operand ( DX:AX ← AX × SRC DX:AX – SRC is Dword operand: EDX:EAX ← EAX × SRC • e.g. ( 11111111B ( * ( 11111111B ( = ( 255D ( * ( 255D ( =65025D =65025D • E.g. MOV BL,5 MOV AL,10 MUL BL ( AX <­­­ 5*10 ( 50 • IMUL SRC ­­­­ signed integer's multiplication. • Format: IMUL REG/MEM • Operation: IMUL SRC – SRC is byte operand ( AX ← AL × SRC AX – SRC is word operand ( DX:AX ← AX × SRC DX:AX – SRC is Dword operand: EDX:EAX ← EAX × SRC • e.g. ( 11111111B ( * ( 11111111B ( = ( ­1 ( * ( ­1 ( =1 • (((( (( CF (( OF ((((((((((((((( • E.g. MOV BL, ­5 MOV AL, 10 IMUL AL ( AX <­­­ (­5)*10=­50 • A Special Immediate 16­bit Multiplication – Signed multiplication, For 80286 and above – IMUL DST, SRC1, SRC2; DST <­­­ SRC1*SRC2 • DST: REG16; SRC1: REG16 or MEM16; SRC2: IMM8 or IMM16 5.2.2 Division 5.2.2 Division • DIV SRC ­­­­ unsigned integer's division. • Format: DIV REG/MEM • Operation: DIV SRC – SRC is byte operand: AX / SRC, AL<­­quotient, AH<­­ remainder – SRC is word operand: DX:AX / SRC, AX<­­quotient, DX<­­ remainder – SRC is Dword operand: EDX:EAX / SRC, EAX<­­quotient, EDX<­­ remainder • None of the flag bits have been defined. • Overflow occurs when a small number divides into a large number. – E.g. AX=3000, DIV 2 – the quotient=3000/2=1500, too large for AL; – A divided error interrupt occurs. • E.g. DIV BL ; DIV word ptr [EDX]; DIV EBP • IDIV SRC ­­­­ signed integer's division. • Format: DIV REG/MEM • Operation: DIV SRC – SRC is byte operand: AX / SRC, AL<­­quotient, AH<­­ remainder – SRC is word operand: DX:AX / SRC, AX<­­quotient, DX<­­ remainder – SRC is Dword operand: EDX:EAX / SRC, EAX<­­quotient, EDX<­­ remainder • None of the flag bits have been defined. • Overflow occurs when a small number divides into a large number. – E.g. AX=­3000, DIV 2 – the quotient=­3000/2=­1500, too large for AL; – A divided error interrupt occurs. • E.g. IDIV BL ; IDIV word ptr [EDX]; IDIV EBP • The remainder have the same sign with the dividend; – E.g. AX=0010H(+16), BL=FDH(­3), IDIV BL – AL=FBH=­5, AH=01 = +1 • E.g. AX=0400H, BL=0B4H – Unsigned division: AX=1024D, BL=180D • DIV BL • Remainder AH=7CH=124D, quotient AL=05H=5D – signed division: AX=+1024D, BL=­76D • IDIV BL • Remainder AH=24H=36D, quotient AL=F3H=­13D (((((((( (((((((( • CBW (((((((( – AL (((((((( AH ((( AH (((( – ((( AL ( 01010101 • (( CBW (( AX ( 00000000 01010101 – (( AL ( 10101010 • (( CBW (( AX ( 11111111 10101010 (((((((( • CWD (((((((( ((( DX – AX (((((((( DX ((( DX ( AX ((((( (((((((( • CWDE (((((((( – AX (((((((( EAX ((( EAX ((((( ((( • CDQ ((((( 4 ((( 1 ((( EDX – EAX (((((((( EDX ((( EDX ( EAX ((84 (( (( 5.4 Basic Logic Instruction 5.4 Basic Logic Instruction • • • • • • AND DST ( SRC ( DST ← DST and SRC DST OR DST ( SRC ( DST ← DST or SRC DST XOR DST ( SRC ( DST ← DST xor SRC DST TEST DST ( SRC ( DST and SRC , affect flag bits. DST and SRC , affect flag bits. NOT OPR ( OPR ← not OPR ( ( OPR (((( ) OPR NEG OPR; OPR ← 2's complement of OPR ( ( OPR (( ) – – – – DST: REG/MEM SRC: REG/MEM/IMM OPR: REG/MEM The NOT instruction don't affect flag bits. – – – CF and OF are always cleared. AF is not defined. SF, ZF, PF is set to 0 or 1 according to result. • All logic instructions (except NOT instruction) affect flag bits. • E.g. AND [BX+4], 00FFH; NOT EDX The Truth Table of logic operation A B A and B A or B A xor B 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 1 1 1 0 • e.g. MOV BL, 11110000B AND BL, 10101010B; 1 1 1 1 0 0 0 0 and 1 0 1 0 1 0 1 0 BL= 1 0 1 0 0 0 0 0 • The AND instruction: to clear some bits of a operand. – E.g. AND AL, 11111100B; clear b1b0 of AL. • The OR instruction: to set some bits of a operand. – E.g. OR AL, 00000011B; set b1b0 of AL. • The XOR instruction: to invert some bits of a operand. – E.g. XOR AL, 00000011B; invert b1b0 of AL. 5.5 Shift and Rotate 5.5 Shift and Rotate • • • • SHL OPR, CNT; OPR is SHifted logically Left for CNT bit. SHR OPR, CNT; OPR is SHifted logically Right for CNT bit. SAL OPR, CNT ; OPR is Shifted Arithmetically Left for CNT bit. SAR OPR, CNT ; OPR is Shifted Arithmetically Right for CNT bit. – OPR : REG/MEM, a 8­, 16­ or 32­bit operand. – CNT: register CL or 8­bit immediate number, 1­­31 • e.g. Unsigned integer*2 Signed integer*2 Unsigned integer/2 Signed integer/2 FIGURE 5­9 5.5.2 Rotate 5.5.2 Rotate • RCL OPR, CNT; OPR Rotates left through carry for CNT bit. • ROL OPR, CNT; OPR Rotates left for CNT bit. • RCR OPR, CNT ; OPR Rotates Right through carry for CNT bit. • ROR OPR, CNT ; OPR Rotates Right for CNT bit. – OPR : REG/MEM, a 8­, 16­ or 32­bit operand. – CNT: register CL or 8­bit immediate number, 1­­31 • e.g. MOV word ptr [ECX+EDX*4+20H], 1234H – scaled­index: EDX*4 – 1­byte displacement: 20H – 2­byte immediate: 1234H 5.6 String Comparisons 5.6 String Comparisons SCAS • The SCAS (string scan) compares AL or AX or EAX with a block of memory. • SCASB: byte comparison, set ZF to 1 or 0 – AL ­ ES:[DI], DI <­­ DI ± 1 – AL ­ ES:[EDI], EDI <­­ EDI ± 1 • SCASW: word comparison, set ZF to 1 or 0 – AX ­ ES:[DI], DI <­­ DI ± 2 – AX ­ ES:[EDI], EDI <­­ EDI ± 2 • SCASD: doubleword comparison, set ZF to 1 or 0 – EAX ­ ES:[DI], DI <­­ DI ± 4 – EAX ­ ES:[EDI], EDI <­­ EDI ± 4 • REPE: REPeat while Equal , enables string instructions (SACAS, CMPS) to repeat execution while equal, the maximal repeat times is CX. • REPNE: REPeat while Not Equal , enables string instructions (SACAS, CMPS) to repeat execution while not equal, the maximal repeat times is CX. format: REPE string­instruction format: REPNE string­instruction operation: operation: (1). if CX=0 or ZF=0, end. (1). if CX=0 or ZF=1, end. (2). CX <­­­ CX ( 1; (2). CX <­­­ CX ( 1; (3). execute string­instruction; (3). execute string­instruction; (4). go to (1). (4). go to (1). • example: REPE scasw ; REPNE scasb; REPNE scasd • Example 5.34: using SCASB to search memory BLOCK for 00H, the memory BLOCK contains 100 byte . • when the program ends, ZF=1 means finding AL’s value, ZF=0 means not finding. CMPS • CMPSB/CMPSW/CMPSD: byte/WORD/DWORD comparison, set ZF to 1 or 0. – DS[SI] ­ ES:[DI], DI <­­ DI ± 1/2/4, SI<­­SI ± 1/2/4 – DS[ESI] ­ ES:[EDI], EDI <­­ EDI ± 1/2/4, ESI<­­ESI ± 1/2/4 • REPE CMPSB; REPE CMPSW; REPE CMPSD • REPNE CMPSB; REPNE CMPSW; REPNE CMPSD • EXAMPLE 5­36 compares two 10­byte string : LINE and TABLE, if a mismatch is found, the repeated comparison ends. – When the comparison ends, ZF=1 means all characters are compared and no mismatch exists; ZF=0 means mismatch exists. ...
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