lec5_roundingmachinebasics

lec5_roundingmachinebasics - Rounding Floating Point...

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Unformatted text preview: Rounding Floating Point Numbers and Basics of Machine-Level Programming Marco Gruteser 331 Computer Architecture and Assembly Language Some slides adapted from Bryant, O’Hallaron, and Nath. 1 Carnegie Mellon IEEE 754 Floating Point Representation   Numerical Form: (–1)s M 2E         Sign bit s determines whether number is negative or positive Significand M normally a fractional value in range [1.0,2.0). Exponent E weights value by power of two Encoding       MSB s is sign bit s exp field encodes E (but is not equal to E) frac field encodes M (but is not equal to M) s exp frac Normalized Encoding Example   Value: Float F = 15213.0;     1521310 = 111011011011012 = 1.11011011011012 x 213 Significand M = frac =   1.11011011011012 110110110110100000000002 Exponent E = Bias = Exp =   13 127 140 = 100011002 Result: 0 10001100 11011011011010000000000 s exp frac Carnegie Mellon Floating Point Operations: Basic Idea   x +f y = Round(x + y)   x ×f y = Round(x × y)   Basic idea     First compute exact result Make it fit into desired precision     Possibly overflow if exponent too large Possibly round to fit into frac Carnegie Mellon Floating Point Addition   (–1)s1 M1 2E1 + (-1)s2 M2 2E2 Assume E1 > E2     E1–E2 (–1)s1 M1 Exact Result: (–1)s M 2E Sign s, significand M:     Result of signed align & add Exponent E:   E1 + (–1)s2 M2 (–1)s M   Fixing If M ≥ 2, shift M right, increment E  if M < 1, shift M left k positions, decrement E by k  Overflow if E out of range  Round M to fit frac precision   Carnegie Mellon Rounding   Rounding Modes (illustrate with $ rounding)             $1.40 Towards zero $1 Round down (−∞) $1 Round up (+∞) $2 Nearest Even (def) $1 $1.60 $1 $1 $2 $2 $1.50 $2.50 –$1.50 $1 $2 –$1 $1 $2 –$2 $2 $3 –$1 $2 $2 –$2 What are the advantages of the modes? Carnegie Mellon Closer Look at Round-To-Even   Default Rounding Mode     Hard to get any other kind without dropping into assembly All others are statistically biased     Sum of set of positive numbers will consistently be over- or underestimated Applying to Other Decimal Places / Bit Positions   When exactly halfway between two possible values     Round so that least significant digit is even E.g., round to nearest hundredth 1.2349999 1.2350001 1.2350000 1.2450000 1.23 1.24 1.24 1.24 (Less than half way) (Greater than half way) (Half way—round up) (Half way—round down) Carnegie Mellon Rounding Binary Numbers   Binary Fractional Numbers       “Even” when least significant bit is 0 “Half way” when bits to right of rounding position = 100…2 Examples Round to nearest 1/4 (2 bits right of binary point) Value Binary Rounded Action Rounded Value 2 3/32 10.000112 10.002 (<1/2—down) 2 2 3/16 10.001102 10.012 (>1/2—up) 2 1/4 2 7/8 10.111002 11.002 ( 1/2—up) 3 2 5/8 10.101002 10.102 ( 1/2—down) 2 1/2   Basics of Machine-Level Programming 9 Intel x86 Processors   Totally dominate laptop/desktop/server market   Evolutionary design       Backwards compatible up until 8086, introduced in 1978 Added more features as time goes on Complex instruction set computer (CISC)   Many different instructions with many different formats       But, only small subset encountered with Linux programs Hard to match performance of Reduced Instruction Set Computers (RISC) But, Intel has done just that!   In terms of speed. Less so for low power. Intel x86 Processors: Overview Architectures X86 ­16 X86 ­32/IA32 MMX SSE SSE2 SSE3 X86 ­64 / EM64t SSE4 Processors 8086 286 386 486 PenEum PenEum MMX PenEum III PenEum 4 PenEum 4E PenEum 4F Core 2 Duo Core i7 IA: oNen redefined as latest Intel architecture Eme Assembly Programmer’s View Memory CPU PC Addresses Registers CondiEon Codes Data InstrucEons Object Code Program Data OS Data Stack   Programmer-Visible State   PC: Program counter Address of next instruction   Called “EIP” (IA32) or “RIP” (x86-64)     Register file     Heavily used program data Condition codes Store status information about most recent arithmetic operation   Used for conditional branching     Memory Byte addressable array   Code, user data, (some) OS data   Includes stack used to support procedures   Compiling Into Assembly C Code int sum(int x, int y) { int t = x+y; return t; } Generated IA32 Assembly sum: pushl %ebp movl %esp,%ebp movl 12(%ebp),%eax addl 8(%ebp),%eax popl %ebp ret Some compilers use instrucEon “leave” Obtain with command /usr/local/bin/gcc –O1 -S code.c Produces file code.s Assembly Characteristics: Data Types   “Integer” data of 1, 2, or 4 bytes     Data values Addresses (untyped pointers)   Floating point data of 4, 8, or 10 bytes   No aggregate types such as arrays or structures   Just contiguously allocated bytes in memory Machine Instruction Example   C int t = x+y;   Code Add two signed integers   Assembly addl 8(%ebp),%eax     “Long” words in GCC parlance   Same instruction whether signed or unsigned Similar to expression: x += y More precisely:   int *ebp; 0x80483ca: 03 45 08 Operands: x: Register y: Memory t: Register int eax; eax += ebp[2] Add 2 4-byte integers  Return   Object %eax M[%ebp+8] %eax function value in %eax Code 3-byte instruction   Stored at address 0x80483ca   Integer Registers (IA32) Origin (mostly obsolete) general purpose %eax %ax %ah %al accumulate %ecx %cx %ch %cl counter %edx %dx %dh %dl data %ebx %bx %bh %bl base %esi %si source index %edi %di destination index %esp %sp stack pointer %ebp %bp base pointer 16 ­bit virtual registers (backwards compaEbility) Moving Data: IA32 %eax   Moving Data %ecx movl Source, Dest:   %edx Operand Types %ebx   Immediate: Constant integer data         Register: One of 8 integer registers         Example: $0x400, $-533 Like C constant, but prefixed with ‘$’ Encoded with 1, 2, or 4 bytes %esi %edi %esp %ebp Example: %eax, %edx But %esp and %ebp reserved for special use Others have special uses for particular instructions Memory: 4 consecutive bytes of memory at address given by register     Simplest example: (%eax) Various other “address modes” movl Operand Combinations Source Dest Src,Dest C Analog Imm temp = 0x4; Reg Reg movl %eax,%edx Mem movl %eax,(%edx) temp2 = temp1; Mem movl Reg movl $0x4,%eax Mem movl $-147,(%eax) Reg temp = *p; movl (%eax),%edx *p = -147; *p = temp; Cannot do memory-memory transfer with a single instruction Simple Memory Addressing Modes  Normal (R) Mem[Reg[R]]   Register R specifies memory address movl (%ecx),%eax  Displacement D(R) Mem[Reg[R]+D] Register R specifies start of memory region   Constant displacement D specifies offset   movl 8(%ebp),%edx Using Simple Addressing Modes void swap(int *xp, int *yp) { int t0 = *xp; int t1 = *yp; *xp = t1; *yp = t0; } swap: pushl %ebp movl %esp,%ebp pushl %ebx movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) popl popl ret %ebx %ebp Set Up Body Finish Using Simple Addressing Modes void swap(int *xp, int *yp) { int t0 = *xp; int t1 = *yp; *xp = t1; *yp = t0; } swap: pushl %ebp movl %esp,%ebp pushl %ebx movl movl movl movl movl movl popl popl ret 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) %ebx %ebp Set Up Body Finish Understanding Swap void swap(int *xp, int *yp) { int t0 = *xp; int t1 = *yp; *xp = t1; *yp = t0; } Offset • • • 12 xp 4 (in memory) yp 8 Stack Rtn adr 0 Old %ebp Register %edx %ecx %ebx %eax Value xp yp t0 t1 -4 Old %ebx movl movl movl movl movl movl %ebp %esp 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 123 456 Understanding Swap Address 0x124 0x120 0x11c %eax Offset %edx 0x114 yp %esi 0x120 0x110 8 0x124 0x10c 4 %ebx 12 xp %ecx Rtn adr 0x108 %ebp %edi 0 0x104 -4 %esp %ebp 0x118 0x104 movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # 0x100 edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 123 456 Understanding Swap Address 0x124 0x120 0x11c %eax %edx Offset 0x124 0x114 yp %esi 0x120 0x110 8 0x124 0x10c 4 %ebx 12 xp %ecx Rtn adr 0x108 %ebp %edi 0 0x104 -4 %esp %ebp 0x118 0x104 movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # 0x100 edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 123 456 Understanding Swap Address 0x124 0x120 0x11c %eax %edx Offset 0x124 %ecx 0x120 0x114 yp 0x120 0x110 8 0x124 0x10c 4 %esi 12 xp %ebx Rtn adr 0x108 %ebp %edi 0 0x104 -4 %esp %ebp 0x118 0x104 movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # 0x100 edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 123 456 Understanding Swap Address 0x124 0x120 0x11c %eax %edx 0x120 %ebx Offset 0x124 %ecx 123 0x114 yp 12 0x120 0x110 xp 8 0x124 0x10c 4 %esi Rtn adr 0x108 %ebp %edi 0 0x104 -4 %esp %ebp 0x118 0x104 movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # 0x100 edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 123 456 Understanding Swap Address 0x124 0x120 0x11c %eax 456 %edx 0x124 %ecx 0x120 %ebx 123 Offset 0x114 yp 12 0x120 0x110 xp 8 0x124 0x10c 4 %esi Rtn adr 0x108 %ebp %edi 0 0x104 -4 %esp %ebp 0x118 0x104 movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # 0x100 edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 456 456 Understanding Swap Address 0x124 0x120 0x11c %eax 45656 4 %edx 0x124 %ecx 0x120 %ebx 123 Offset 0x114 yp 12 0x120 0x110 xp 8 0x124 0x10c 4 %esi Rtn adr 0x108 %ebp %edi 0 0x104 -4 %esp %ebp 0x118 0x104 movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # 0x100 edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 456 123 Understanding Swap Address 0x124 0x120 0x11c %eax 456 %edx 0x124 %ecx 0x120 %ebx 123 Offset 0x114 yp 12 0x120 0x110 xp 8 0x124 0x10c 4 %esi Rtn adr 0x108 %ebp %edi 0 0x104 -4 %esp %ebp 0x118 0x104 movl movl movl movl movl movl 8(%ebp), %edx 12(%ebp), %ecx (%edx), %ebx (%ecx), %eax %eax, (%edx) %ebx, (%ecx) # # # # # # 0x100 edx ecx ebx eax *xp *yp = = = = = = xp yp *xp (t0) *yp (t1) t1 t0 Complete Memory Addressing Modes   Most General Form D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Constant “displacement” 1, 2, or 4 bytes   Rb: Base register: Any of 8 integer registers   Ri: Index register: Any, except for %esp     Unlikely   S: you’d use %ebp, either Scale: 1, 2, 4, or 8 (why these numbers?)   Special Cases (Rb,Ri) D(Rb,Ri) (Rb,Ri,S) Mem[Reg[Rb]+Reg[Ri]] Mem[Reg[Rb]+Reg[Ri]+D] Mem[Reg[Rb]+S*Reg[Ri]] Next Class     Continuing assembly Language Practice Problems remainder 2.4 - 3.1 31 ...
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This document was uploaded on 10/20/2011.

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