lec11_instruction_encoding

lec11_instruction_encoding - 1 CS:APP2e Carnegie Mellon...

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Unformatted text preview: 1 CS:APP2e Carnegie Mellon Instruction Encoding and Decoding (in Y86) Marco Gruteser 331 Computer Architecture and Assembly Language Carnegie Mello Slides adapted from Bryant, OHallaron, and Nath. 2 CS:APP2e %eax %ecx %edx %ebx %esi %edi %esp %ebp ZF SF OF Simplified Y86 Processor State n Program Registers l Same 8 as with IA32. Each 32 bits n Condition Codes l Single-bit flags set by arithmetic or logical instructions ZF: Zero SF:Negative OF: Overflow n Program Counter l Indicates address of next instruction n Program Status l Indicates either normal operation or some error condition n Memory l Byte-addressable storage array l Words stored in little-endian byte order RF: Program registers CC: Condition codes PC DMEM: Memory Stat: Program status 3 CS:APP2e Y86 Instruction Set #1 Byte 1 2 3 4 5 pushl rA A rA 8 jXX Dest 7 fn Dest popl rA B rA 8 call Dest 8 Dest cmovXX rA, rB 2 fn rA rB irmovl V, rB 3 8 rB V rmmovl rA, D(rB) 4 rA rB D mrmovl D(rB), rA 5 rA rB D OPl rA, rB 6 fn rA rB ret 9 nop 1 halt 4 CS:APP2e Y86 Instructions Format n 1 6 bytes of information read from memory l Can determine instruction length from first byte l Not as many instruction types, and simpler encoding than with IA32 n Each accesses and modifies some part(s) of the program state 5 CS:APP2e Y86 Instruction Set #2 Byte 1 2 3 4 5 pushl rA A rA 8 jXX Dest 7 fn Dest popl rA B rA 8 call Dest 8 Dest cmovXX rA, rB 2 fn rA rB irmovl V, rB 3 8 rB V rmmovl rA, D(rB) 4 rA rB D mrmovl D(rB), rA 5 rA rB D OPl rA, rB 6 fn rA rB ret 9 nop 1 halt rrmovl 7 cmovle 7 1 cmovl 7 2 cmove 7 3 cmovne 7 4 cmovge 7 5 cmovg 7 6 6 CS:APP2e Y86 Instruction Set #3 Byte 1 2 3 4 5 pushl rA A rA 8 jXX Dest 7 fn Dest popl rA B rA 8 call Dest 8 Dest cmovXX rA, rB 2 fn rA rB irmovl V, rB 3 8 rB V rmmovl rA, D(rB) 4 rA rB D mrmovl D(rB), rA 5 rA rB D OPl rA, rB 6 fn rA rB ret 9 nop 1 halt addl 6 subl 6 1 andl 6 2 xorl 6 3 7 CS:APP2e Y86 Instruction Set #4 Byte 1 2 3 4 5 pushl rA A rA 8 jXX Dest 7 fn Dest popl rA B rA 8 call Dest 8 Dest rrmovl rA, rB 2 fn rA rB irmovl V, rB 3 8 rB V rmmovl rA, D(rB) 4 rA rB D mrmovl D(rB), rA 5 rA rB D OPl rA, rB 6 fn rA rB ret 9 nop 1 halt jmp 7 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6 8 CS:APP2e Encoding Registers Each register has 4-bit ID n Same encoding as in IA32 Register ID 15 (0xF) indicates no register n Will use this in our hardware design in multiple places %eax %ecx %edx %ebx %esi %edi %esp %ebp 1 2 3 6 7 4 5 9 CS:APP2e Instruction Example Addition Instruction n Add value in register rA to that in register rB l Store result in register rB l Note that Y86 only allows addition to be applied to register data n Set condition codes based on result n e.g., addl %eax,%esi Encoding: 60 06 n Two-byte encoding l First indicates instruction type l Second gives source and destination registers addl rA, rB 6 rA rB Encoded Representation Generic Form 10 CS:APP2e Move Instruction Examples...
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lec11_instruction_encoding - 1 CS:APP2e Carnegie Mellon...

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