lec12-sequential_fin

Lec12-sequential_fin - Carnegie Mellon Carnegie Mello Sequential Processor Implementation Marco Gruteser 331 Computer Architecture and Assembly

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– 1 – CS:APP2e Carnegie Mellon Sequential Processor Implementation Marco Gruteser 331 Computer Architecture and Assembly Language Carnegie Mello Slides adapted from Bryant, O’Hallaron,  and Nath.
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– 2 – CS:APP2e Building Blocks Combinational Logic n Compute Boolean functions of inputs n Continuously respond to input changes n Operate on data and implement control Storage Elements n Store bits n Addressable memories n Non-addressable registers n Loaded only as clock rises Register file A B W dstW srcA valA srcB valB valW Clock A L U fun A B MUX 0 1 = Clock
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– 3 – CS:APP2e Hardware Control Language n Very simple hardware description language n Can only express limited aspects of hardware operation l Parts we want to explore and modify Data Types n bool : Boolean l a , b , c , … n int : words l A , B , C , … l Does not specify word size---bytes, 32-bit words, … Statements n bool a = bool-expr ; n int A = int-expr ;
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– 4 – CS:APP2e HCL Operations n Classify by type of value returned Boolean Expressions n Logic Operations l a && b , a || b , !a n Word Comparisons l A == B , A != B , A < B , A <= B , A >= B , A > B n Set Membership l A in { B, C, D } » Same as A == B || A == C || A == D Word Expressions n Case expressions l [ a : A; b : B; c : C ] l Evaluate test expressions a , b , c , … in sequence l Return word expression A , B , C , … for first successful test
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– 5 – CS:APP2e Stage Computation: Arith/Log. Ops n Formulate instruction execution as sequence of simple steps n Use same general form for all instructions OPl rA, rB icode:ifun  M1[PC] rA:rB  M1[PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory R[rB]  valE Write back Write back result PC  valP PC update Update PC
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– 6 – CS:APP2e Executing rmmovl Fetch n Read 6 bytes Decode n Read operand registers Execute n Compute effective address Memory n Write to memory Write back n Do nothing PC Update n Increment PC by 6 rmmovl rA, D(rB) 4 0 rA rB D
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– 7 – CS:APP2e Stage Computation: rmmovl n Use ALU for address computation rmmovl rA, D(rB) icode:ifun  M1[PC] rA:rB  M1[PC+1] valC  M4[PC+2] valP  PC+6 Fetch Read instruction byte Read register byte Read displacement D Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB + valC Execute Compute effective address M4[valE]  valA Memory Write value to memory Write back PC  valP PC update Update PC
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– 8 – CS:APP2e Computed Values Fetch icode Instruction code ifun Instruction function rA Instr. Register A rB Instr. Register B valC Instruction constant valP Incremented PC Decode srcA Register ID A srcB Register ID B dstE Destination Register E dstM Destination Register M valA Register value A Execute n valE ALU result n Cnd Branch/move flag Memory n valM Value from memory
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– 9 – CS:APP2e SEQ Hardware Key n Blue boxes: predesigned hardware blocks l E.g., memories, ALU n Gray boxes: control logic
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This document was uploaded on 10/20/2011.

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Lec12-sequential_fin - Carnegie Mellon Carnegie Mello Sequential Processor Implementation Marco Gruteser 331 Computer Architecture and Assembly

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