LOGIC15_r2

# LOGIC15_r2 - Chapter 15 Reduction of State Tables State...

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Chapter 15 Reduction of State Tables State Assignment

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Ex Rework Z=1 if x=0101 or 1001 occurs. The network resets after every four inputs. Set enough states to remember the first three bits of every possible input sequence. Then when the fourth bit come in, we can determine the correct output and reset the network to the initial state. § Elimination of Redundant States
Input Sequence Present State Next State X=0 X=1 Present Output X=0 X=1 reset A B C 0 0 0 B D E 0 0 1 C F G 0 0 00 D H I 0 0 01 E J K 0 0 10 F L M 0 0 11 G N P 0 0 000 H A A 0 0 001 I A A 0 0 010 J A A 0 1 011 K A A 0 0 100 L A A 0 1 101 M A A 0 0 110 N A A 0 0 111 P A A 0 0

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Note For state H, the next state is A and output =0 For state I, the next state is A and output =0 There is no way of telling states H I apart and we can replace I with H where it appears in the next state portion of the table. Equivalent States Two states are equivalent if there is no way of telling then apart from observation of the network inputs and outputs. Consider two sequential networks, one is started in state p and the
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## This note was uploaded on 10/23/2011 for the course EE 101 taught by Professor Wang during the Spring '11 term at Illinois State.

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LOGIC15_r2 - Chapter 15 Reduction of State Tables State...

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