lecture03 - EE 338L CMOS Analog Integrated Circuit Design...

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S. Yan, EE 338L Lecture 3 1 EE 338L CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances Small Signal Models, and Passive Components MOS Capacitances Type of MOS transistor capacitors Depletion capacitance (pn junction capacitance) Gate-channel or gate-substrate capacitance Gate-source and gate-drain overlap capacitance Or, Intrinsic capacitances (that MOS transistor operation relies on) Extrinsic capacitances (parasitic capacitances)
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S. Yan, EE 338L Lecture 3 2 Junction Capacitance Gate-Channel and Gate-Substrate Capacitance Cut-off Triode Saturation Gate-channel 0 C ox WL 2/3 C ox WL Gate-substrate + WL C WL x ox si d 1 1 ε +C GB,ov C GB,ov C GB,ov Gate-Source and Gate-Drain Capacitance Cut-off Triode Saturation Gate-Source C GS,ov ½C ox WL+C GS,ov 2/3 C ox WL+C GS,ov Gate-Drain C GD,ov ½C ox WL+C GD,ov C GD,ov Gate-Source and Gate-Drain Overlap Capacitance (C3 and C4 in the following figure)
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S. Yan, EE 338L Lecture 3 3 CGSO W C OV GS = , CDSO W C OV GD = , Variation of gate-source and gate-drain capacitance [allen02]
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S. Yan, EE 338L Lecture 3 4 NMOS transistor small signal model For a MOS transistor, the drain current is a function of V GS , V BS , and V DS . () + = triode) (in , 2 ) ( ) saturation (in ), 1 ( 2 1 off) (cut , 0 2 2 DS DS T GS p DS T GS p D V V V V L W K V V V L W K I λ where ox ox ox p t C K ε µ = = and ) | 2 | | 2 | ( 0 F SB F T T V V V φ γ + + = . Or, [] {} + + + + + = triode) (in , 2 ) | 2 | | 2 | ( ) saturation (in ), 1 ( ) | 2 | | 2 | ( 2 1 off) (cut , 0 ) , , ( 2 0 2 0 DS DS F SB F T GS p DS F SB F T GS p DS BS GS D V V V V V L W K V V V V L W K V V V I Thus, DS DS D BS BS D GS GS D D V V I V V I V V I I + + = we define g m as GS D V I , g mb as BS D V I , and g ds as DS D V I .
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S. Yan, EE 338L Lecture 3 5 g ds g m v gs g mb v bs v d v g v s v b v d : drain terminal voltage v g : gate terminal voltage v s : source terminal voltage v b : bulk terminal voltage v gs = v g -v s v bs = v b s M1 v G v D v S v B Symbol Small signal model I D Here v b is shortened from v bulk . Some other times, v b means v bias . If we include the pn junctions and MOS capacitances, we have Note that, g o is another name of g ds . Saturation region (strong inversion): V DS > V GS V T , or V D > V G V T Parameter Considering ( DS V λ + 1 ) Assuming 1 1 = + DS V in some steps D I ) ( ) ( DS T GS P V V V L W K + 1 2 1 2 2 2 1 ) ( T GS P V V L W K m g constant keep and VBS VDS GS D V I
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S. Yan, EE 338L Lecture 3 6 ) )( ( DS T GS P V V V L W K λ + 1 ) ( T GS P V V L W K ) ( DS P D V L W K I + 1 2 L W K I P D 2 T GS D V V I 2 T GS D V V I 2 constant keep and constant keep and VDS VGS BS T T D VDS VGS BS D V V V I V I
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This note was uploaded on 10/23/2011 for the course SDASD 102 taught by Professor Dsfas during the Spring '11 term at Baptist Bible PA.

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lecture03 - EE 338L CMOS Analog Integrated Circuit Design...

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