lecture04 - EE 338L CMOS Analog Integrated Circuit Design...

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S. Yan, EE 338L Lecture 4 1 EE 338L CMOS Analog Integrated Circuit Design Lecture 4, Single-Stage Amplifiers (1) We will cover the following amplifier structures in the future weeks. B V B I in V DD V DD V out V L R in V out V DD V DD V L R S R in V Common Source Common Gate Common Drain ( Source Follower) Source Degeneration L R B I out V out V in V M1 M2 DD V B V out V Cascode Configuration ( Common Source + Common Gate ) M2 M1 DD V 1 out V 2 out V in V B I Differential Pair CG CS or CG ? L R L R L R in V
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S. Yan, EE 338L Lecture 4 2 Large signal and small signal concepts: Assuming + + + + + = n n x x a x x a x x a a y ) ( ) ( ) ( 0 2 0 2 0 1 0 When 0 x x , we have ) ( ) ( ) ( 0 0 0 x x dy dx x y x y x x + = = ) ) ( ( )) ( ( 0 1 0 x t x t x y + = α ) ) ( ( ) ( 0 1 0 x t x t y + = Therefore, for small signal analysis, we assume y and x are small enough, thus we can treat them as if they are linearly dependent with each other. Basically, small signal analysis is simply a linearized approximation of a non- linear circuit or system. In small signal analysis, we usually only care about y and x , and ignore the DC (the constant term) values of the variables. Linearized models could lead to much simpler analysis and can satisfy most of our needs for When the amplitude of x(t) is large enough, and high order terms in the equation can not be neglected. Then large signal analysis becomes necessary.
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S. Yan, EE 338L Lecture 4 3 Performance trade-offs in amplifier design: Noise Linearity Power Dissipation Input/Output Impedance Speed Voltage Swing Gain Supply Voltage Common Source Stage Load M1 Load In Saturation In Triode V in V out V DD Example1: Common source amplifier with resistive load.
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S. Yan, EE 338L Lecture 4 4 In the following analysis, we ignore channel length modulation effect for simplicity. 1) When T in V V < , M1 is in cut-off region DD L D DD out D V R I V V I = = = 0 2) When T in V V > , and 1 in in V V < (We define the input voltage when M1 is at the boundary of saturation and triode regions as 1 in V ), M1 is in saturation region. 2 ) ( 2 1 T GS P D V V L W K I = Thus L T in P DD L D DD out R V V L W K V R I V V = = 2 ) )( ( 2 1 Note that when M1 is at the boundary of saturation and triode regions DS T GS V V V = , we have out T in V V V = 1 . 1 in V is given by the following equation, T DD in V V V + + = α 2 1 4 1 1 , where L P R L W K = ) ( 2 1 3) When 1 in in V V > , M1 is in triode region. ] 2 ) [( 2 DS DS T GS P D V V V V L W K I = Thus Vin Vout V T T GS DS V V V = Vin1 in V L R DD V out V M1
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S. Yan, EE 338L Lecture 4 5 L out out T in P DD L D DD out R V V V V L W K V R I V V = = ] 2 ) [( 2 out V can be obtained as a function of in V through solving the above equation. As GS V has less control on D I when transistor M1 works in triode region, we usually leave M1 in saturation for a large voltage gain.
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This note was uploaded on 10/23/2011 for the course SDASD 102 taught by Professor Dsfas during the Spring '11 term at Baptist Bible PA.

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lecture04 - EE 338L CMOS Analog Integrated Circuit Design...

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