This preview shows pages 1–4. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: 1 BILKENT UNIVERSITY ENGINEERING FACULTY DEPARTMENT OF COMPUTER ENGINEERING CS 224 – Spring 2010 Group 2B: Project #2 Preliminary Design Report Tuba Kesten 20801197 (507) 2595775 Section 2 kesten@ug.bilkent Efe Budak 20701423 (554)3615075 Section 2 e_budak@ug.bilkent Gizem Sarıkaya 20701439 (535)8376302 Section 2 sarikaya_g@ug.bilkent HONOR PLEDGE: We promise that all work contained in this Group Contact Report is the product of our own efforts, and that we received no help from other students in other groups. Signed: ___________________ Signed:___________________ Signed: ___________________ Other groups: Instructor/TA help: Books: Internet URLs: Other: Submission date: 26/04/2010 2 1 ) 1 st SubSection 1.1) RTL Descriptions (add, and, nor, or, slt, sub) Figure 1.1 Field bit position of general R Type →add rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] ← R[rs] + R[rt] Add operation PC ← PC + 4 Calculate the next address →and rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] ← R[rs] & R[rt]; And operation PC ← PC + 4; Calculate the next address →or rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] ← R[rs]  R[rt]; Or operation PC ← PC + 4; Calculate the next address →nor rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] ← ~(R[rs]  R[rt]); Nor operation PC ← PC + 4; Calculate the next address →slt rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] ← (R[rs] < R[rt]) ? 1:0; Slt operation PC ← PC + 4; Calculate the next address →sub rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] ← R[rs]  R[rt]; Subtract operation PC ← PC + 4; Calculate the next address OP=0 rs rt rd sa funct 6 5 5 5 5 6 3 1.2) Explanation We take the instructor from PC box into instructor memory and calculate the next instructor by an ALU. After taking the instructor from instruction memory unit, we send the first six bits of the instructor, which is called opcode, to the control unit. Following five bits of the instructor, which are called rs, are the codes for the address of the first register that is read and sent to ALU. Address of the second register that is sent to ALU for operation is coded in the following five bits of the instructor, which are called rt. The following five bits of the instructor, which are called rd, are the codes for the address of the register that will get the result of the ALU. Last six bits of the instructor, which are called function, are used to decide which operation will be done on ALU. ALU control unit gets function and decide on the required operation. After ALU operation, result is sent to the register file and written on register rd. Hardware components Control Signals PC regWrite adder 1ALU ALUOp Instruction Mem....
View
Full
Document
 Spring '11
 Pablo

Click to edit the document details