# 3 - Chapter 3 Logic Gates, Latches and Flip-Flop 3.1 Logic...

This preview shows pages 1–5. Sign up to view the full content.

1 Chapter 3 Logic Gates, Latches and Flip-Flop 3.1 Logic Gates NOT (inverter) Truth table A NOT gate produces an output that is an inverse or a complement of its input. The complement of a variable is indicated by a bar or a prime over the variable. An inversion bubble denotes logical inversion . In terms of signals and active levels, a bubble is used to indicate an active-low signal. An absence of a bubble indicates an active-high signal. A signal is said to be asserted when it is at its active level. A signal is said to be negated/deasserted when it is at its non-active level. Preferred usage of symbols: F X X X X - Positive logic representation is used throughout. - Distinctive-shape symbols for logic gates are used. Refer Floyd for rectangular outline symbols. inversion bubble F = X or X logic equation

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 AND OR NAND NOR X X X X Not incorrect but improper usage F F = X Y F = X + Y F An OR gate produces a 1 if one or more of its inputs are 1 An AND gate produces a 1 if all of its inputs are 1 F = ( X Y ) F = ( X+Y ) F F Logical operator
3 Exclusive-OR (XOR) Exclusive-NOR (XNOR) 3.2 Latches and Flip-Flops Sequential circuits have outputs that depend on both the present inputs and the past sequence of inputs. To be able to remember past inputs, sequential circuits contain memory devices called latches and flip-flops . Both latches and flip-flops can be in one of two stable states (bistable) and have one or more inputs that can be used to change the outputs. Flip- flops have clock inputs whereas latches have no clock inputs. 3.2.1 Set-Reset Latch Consider the cross-coupled NOR gates circuit below: X Y F = ( X Y) = X Y + XY X Y F = X Y = X Y+XY S R Q Q

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4 If S = 1, R = 0, then Q = 0 and Q = 1. If S = 0, R = 1, then Q = 0 and Q = 1. If R = S = 0, if Q was 1 previously, then Q = 0 and Q remains 1.
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 10/23/2011 for the course BME KUEU taught by Professor Ting during the Fall '10 term at Universiti Teknologi Malaysia.

### Page1 / 14

3 - Chapter 3 Logic Gates, Latches and Flip-Flop 3.1 Logic...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online