Homework2_solution

# Homework2_solution - PROBLEM 1) NAND/NOR A) To give a 2:1...

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PROBLEM 1 ) NAND/NOR A) To give a 2:1 PMOS to NMOS ratio, the CMOS NAND must look like The resistors above are scaled with respect to the minimum sized inverter which is assumed to have a 2:1 ratio. The capacitance at the internal nodes for the NAND gate is int,1 , , , , int, , , , , 4 2 2 2 6 0.23 4 0.5 3.3 4 4 2 2 4 0.23 4 0.39 2 0.5 2 0.79 5    gd N gs N db N sb N Qg d Ng d Pd b Nd b P CC C C C f F f Ff F C C C C C f F f F f F The capacitance at the internal nodes for the NOR gate is int,1 , , , , int, , , , , 4 2 2 2 6 0.39 4 0.8 5.5 4 4 2 2 40 .23 .39 20 .5 .79 5  gd P gs P db P sb P Q gd N gd P db N db P CCC f F f F CCCCC fF fF fF fF fF The on-switch resistance is 5.5 7.5 eqn eqp Rk and are compared to the minimum size inverter. B) Propagation delays for NAND All six input conditions that result in a transition will have a unique propagation delay. First, for the high-to-low transitions. The internal node can be pre-charged to ground Vdd

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## This note was uploaded on 10/24/2011 for the course ECON 165 taught by Professor Berman,e during the Spring '08 term at UCSD.

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Homework2_solution - PROBLEM 1) NAND/NOR A) To give a 2:1...

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