Homework4_solution_updateSP10

Homework4_solution_updateSP10 - Problem 1. A) B) For the...

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Problem 1. A) B) For the carry circuit we can optimal size each gate. 23 4 5 4 5 20 20 20 ,, 1 , ,1 . 4 9 33 3 3 9 9 9 NAND NAND ggF G H G F B h      , 2 3 2 1.49 7.98 pCo po tP N h t t t    C) For the sum circuit,     , 12, 12, 10 12 10 12 132 XOR XOR p S po po po pgF t t p f g t t , since as a single gate no sizing is possible. In my estimation, the sum circuit that I have chosen is much slower (even if F=1). D) The sizing of the PMOS devices might seem tricky at first. Note that both A and B must be true to pull up node X when the carry-in is true. Alternatively, consider the case where either A or B is true and the carry-in is false. In either case you will have a series combination of a device of size x with a device of size x/2.Therefore, the PMOS devices should satisfy
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,, , 3 22 eq p eq p eq p RRR x xx  and clearly each series transistors should be 6 and the parallel transistors should be 6.
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Homework4_solution_updateSP10 - Problem 1. A) B) For the...

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