00ECE108IdealInverter_noisemargins

00ECE108IdealInverter_noisemargins - INTRODUCTION TO...

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Unformatted text preview: INTRODUCTION TO INVERTERS A THOUGHT EXPERIMENT Source Liquid flow (current) Output Level sensor Pull up valve Reservoir Pull Down valve Drain FLUIDIC INVERTER CHAIN Source Liquid flow (current) Pull up valve Source Pull up valve Liquid flow (current) Level sensor Reservoir Level sensor Reservoir Pull Down valve Pull Down valve Drain Drain FLUIDIC vs. ELECTRONIC INVERTER Source Liquid flow (current) Pull up valve Level sensor Reservoir VDD Electron flow Current) pull up Pull Down valve Output voltage C Drain pull down Reservoir of electrons Ideal Electronic Inverter The simplest digital electrical logic gate is an inverter. • An inverter consists of two electrical devices a pull-up device and a pulldown device connected in a circuit to a capacitor. The pull-up device also referred to as the load can be a 2-terminal or 3-terminal, passive or active device. The pull-down or the driver is a 3-terminal device or a switch. • An inverter that has an ideal switch as the pull-down device is referred to as an ideal inverter. It exhibits ideal characteristics Ideal Pull-down: VIN > VT ->IS = VIN < VT ->IS = 0 P I out V IN > V T V out V IN < V T The Ideal Inverter GOAL OF AN INVERTER Invert received information bit and relay it to the next stage accurately and rapidly with minimal energy loss • Rail to rail (VDD-GND) switching • Sharp transfer characteristics • Negligible rise and fall times TRANSFER CHARACTERISTICS NMH = NML =VDD/2 Zero propagation delay Fanout = ∞ TIME RESPONSE Ideal Resistive Pull-Up Inverter To analyze the inverter operation we need to write the device and circuit equation and solve them A. DEVICE EQUATIONS: Vp Pull-up: VR = RIR IR R Ideal Pull-down: VIN > VT ->IS = ∞ Vout VIN < VT ->IS = 0 IS V in B. CIRCUIT EQUATIONS: Voltage: Vout = VP - RIR Current: Iout = IS = IR To find parameters of interest, we need to Equate the currents of the pull-up and pull-down devices LOAD LINE and I-V CHARACTERISTICS OF AN IDEAL RESISTIVE LOAD INVERTER: (Iout - Vout) I out IR I out 1/R VIN>VT Vout Pull up V IN > V T Load line (- 1 slope) R VR VIN<VT Pull down Vp - Vout R VP Vout V IN < V T I-V characteristics and Load Line Vout = VP -RIout => Iout = -1/R ( Vout - VP) Load Line Equation • • • The Load Line (LL) provides information about the pull-up and the power supply The behavior of the inverter can then be described with the LL equation together with the output I-V characteristics of the pull-down in the form Iout = f(Vout) generally a non-linear relation. The output for a given input or the points on a transfer characteristics of the inverter can then be calculated by Intersecting the LL with driver output I-V or ó equating load and driver currents IDEAL TRANSFER CHARACTERISTICS : (Vout - Vin) • Transfer characteristics relate the output signal levels to the input signal levels. Its shape strongly reflects the characteristics of the devices used in the inverter circuit. • An ideal transfer characteristic exhibits two well defined logic states: “true”, “high” or “1” state and “false, “low” or “0” state. A sharp transition exists between the logic states and is referred to as the inverter threshold Vinv Vou t VP V in v V in Non Ideal Transfer Charateristics of a real inverter 5.0 4.0 NM L 3.0 Vout (V) 2.0 VM NM H 1.0 0.0 1.0 2.0 3.0 Vin (V) 4.0 5.0 NON-IDEAL INVERTER In practice the pull-down device behaves differently than an ideal switch. It generally exhibits a leakage current in the off state, a finite resistance in the on state and a transition region where the switch can neither be considered as ON or OFF. This deviation from ideality leads to non-ideal transfer characteristics TYPICAL TRANSFER CHARACTERISTICS Non-ideal pull-downs lead to transfer characteristics that differ significantly from an ideal one exhibiting • Wider transition region, and • VOH < VP , and VOL>0. =>Logic levels are not well defined To deal with non-ideal characteristics we define noise margins . When operated within the noise margins the behavior of the inverter can be reasonably close to that of an ideal inverter V DD dVo * V OH =-1 dV i V iH V iL dVo =-1 dV i * V OL * V OL V* iL V* iH * VOH V DD NOISE MARGINS VIH Both input and output axis have same units VOL= VIL Noise margin is the maximum noise voltage added to the input signal that does not cause an undesirable change at the output. • Low input Vin < V*IL • Transition V*IL< Vin < V*IH • High input Vin > V*IH VDD dV o =-1 dV i * VOH dV o =-1 dV i * VOL * VOL * ViL NML = V*IL -V*OL NMH = V*OH -V*IH * V iH * VOH VDD NOISE MARGINS - LOGIC REGENERATION Assumptions: •Both inverters have identical VTC •Both input and output axis have same units VIH VOL= VIL VOH* VOL* NML VOL* VIL* NMH VIH* VOH* LOGIC REGENERATION VIH VOL= VIL VOH* VOL* NML VOL* VIL* NMH VIH* VOH* LOGIC REGENERATION VOH= VIH VIL VOH* VOL* NMH NML VOL* VIL* VIH* VOH* LOGIC REGENERATION VIH VOL= VIL VOH* VOL* NML VOL* VIL* NMH VIH* VOH* IMPACT OF VTC ON NOISE MARGINS VOH* VOH* VOL* VOL* NML NMH IMPACT OF VTC ON NOISE MARGINS VOH* VOH* VOL* VOL* NML NMH=0 IMPACT OF VTC ON NOISE MARGINS VOH* VOH* VOL* VOL* NML NMH=0 IMPACT OF VTC ON NOISE MARGINS VOH* VOH* VOL* VOL* NML NMH< 0 VIH VOL= VIL Non Ideal speed response Typically switching does not occur instantaneously • Rise and fall times are finite • Leading to a significant inverter propagation delay V in 50% Ideal speed response with Negligible rise and fall time And no propagation delay t V out tpHL tpLH 90% 50% t 10% tf tr Bit Error Rate • • BER is closely related to the distortion introduced by the inverter including finite rise and fall times, overshoots and signal jitter. One way to measure BER is through eye diagrams that are obtained by integrating the output of an inverter that is fed by a random sequence of bits that is sufficiently long. By looking at the closing of the eye one can approximately determine the BER. A direct measurement can also be performed by counting the errors at the output of the inverter. This can take a very very long time and is generally only practiced in communication circuits where the BER is around 10-9 and bit rates exceed 1Gb/s Speed Response -Bit Error Rate - Eye Diagram V in V out 90% 10% t σ1 Vdd m1 0V σ0 t BER = Q m1 - m0 σ1 + σ0 m0 ...
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