04ECE108ch4MOSInvpresentation

04ECE108ch4MOSInvpresentation - ECE108 ESENER 4. 1 4....

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Unformatted text preview: ECE108 ESENER 4. 1 4. TWO-TERMINAL PULL-UP MOS INVERTERS ________________________________________________________________________________________________________________ 4.1. Enhancement Mode MOS as a Pull-up Device Drain Diffusion D Metal well oxide contact S G Gate Oxide Source Diffusion Gate connected to drain ⇒ VGS = VDS . Drain current cannot flow unless VDS > VT . VDS > VGS − VT always saturated since VDS > VDS − VT When used as a load VGSL = VDD − Vout VDS =VGS-VT ID VGS =VDS non-linear resistor VG2 VG1 VT VDS ID ID = k (VDD − VT )2 2 k 2 I D = (VDD − Vout − VT ) 2 non-linear resistor VG2 VG1 VDD - V T VDS Esener ECE 108 4. 2 4.2. Saturated Pull-up Inverter ______________________________________________________________________________________________________________ VDD L D • Subscript L will denote load (pull-up) transistor characteristics. • Subscript D will denote driver (pull-down) transistor characteristics. We define the ßr ratio of a MOS inverter as W µ DCox D LD k W L βr ∆ D = Assume µ D = µ L ; CoD = CoL β r = kL µ C W LDWL L ox L L L which is similar to the factor B defined for resistive load inverter. However ßr is dimensionless. In this particular case ßr is a geometrical ratio. In general this assumption is true for devices of the same type within the same chip. For better VTC we want high gain and therefore large ßR: Driver => Short and Wide Load => Long and Narrow Esener ECE 108 4.2.1. 4. 3 VTC Analysis of saturated pull-up inverter 4.2.1.1. Driver saturated-Load saturated Vin< VGS* For load transistor: VGSL = VDD − v out = VDSL I DL kL = (VDD − Vout − VTL )2 2 VDD L D For the driver transistor (v in > VTD ) V I GSD DD = = v in , VDSD = v out kD (v in − VTD )2 2 then letting I DL = I DD v out = 1 −β r 2 (v in − VTD ) + (VDD − VTL ) For Vin = 0 Vout = VDD - VTL For enhancement load inverter the output high is always one VT below the power supply level Esener ECE 108 4. 4 For a sharp transition region 1 dv out = −β r 2 larger β r is preferred dv in At the saturation-linear transition of the driver (VGSD* = vin*) VDSD = VGSD − VTD ⇒ v out = v in − VTD (inserting into the above equation) VDD − VTL v * = V TD + in 1 βr 2 1+ ( and v * out = VDD − VTL 1 βr 2 1+ ( ) ) Esener ECE 108 4. 5 4.2.1.2. Driver linear - Load Saturated Vin> VGS* * For v in > Vin the driver is linear I VDD DD 2 VDS = k D (VGS − VTD )VDS − 2 2 vout = k D (Vin − VTD )vout − 2 L and for the load device D I Letting DL = kL 2 I DL = I DD [ ( (V DD − vout − VTL )] ) 2 v 2 (1 + β r ) − v out 2(VDD − VTL ) + 2β r Vin − VTD + (VDD − VTL ) 2 = 0 out Esener ECE 108 4. 6 A Numerical Example Assume NMOS Enhancement mode devices, VTL = cst. and assume VTD = V TL = 2 V β r = 25 V DD = 7 V Find V OH : V OH = VDD − VTL = 7V − 2 V = 5V Find V OL Let v in VDD L = 5V (Driver linear ) 26 v out − 160 v out + 25 = 0 V OL = v out = 0.16 V 2 D ∆ v out = VOH − VOL = 4.86V Find noise margin: For VinL and in a saturated load inverter there is a sharp transition in the VTC and VinL* corresponds to VTD For VinH* we need to differentiate Vin vs Vout when the driver is linear. Using [ ( )] v 2 (1+ β r ) − v out 2(VDD − VTL ) + 2β r Vin − VTD + (VDD − VTL ) 2 = 0 out Esener ECE 108 4. 7 v 2 + 3.46 vout + 0.96 v in = out 1.93vout dvin 0.50 = 0.52 − 2 = −1 ⇒ vout = 0.573V dv out vout ⇒ vin = 2.97V NM H = 5 − 2.97 = 2.03V ; NM L = 2 − 0.573 = 1.427V 7V VOH=5V SLOPE=-5 V*OL VOL=.16 .57 2 2.97 NML NMH 5V 7V vin Esener ECE 108 4. 8 4.3. DEPLETION LOAD MOS INVERTER ___________________________________________________________________ 4.3.1. NMOS depletion mode transistor as a load VGS = 0 D V LINEAR : I D ID SAT : 2 (k/2)VT ID T <0 2 VDS = k − V T VDS − 2 ( ) k = −VT 2 2 = k2 VT 2 VDS ≥ VGS − VT SAT S -vT ⇒ VDS ≥ − VT SAT VDS ≤ − VT LINEAR Esener ECE 108 4.3.2. 4. 9 Depletion load inverter VDD ID Load Line Driver γ =0 γ=0 VDD Vout • Depletion load provides non-linear resistance: • Low resistance when the output is high => βr will be small and the output will charge fast to its high level • High resistance when the output is mid range and low => βr will be effectively very high in these conditions leading to sharp transition and very low output low This inverter type will provide • Better dynamic range VOH = VDD; VOL -> 0, Sharper transition and • Faster speed Esener ECE 108 4.3.3. 4. 10 VTC analysis A. TD OFF, TL LINEAR/OFF Vin < VTD ~ I DD = I DL = 0 2 V DSL 0 = k L − VTL V DSL − 2 ( ) V DSL = 0 ⇒ V DSL = − 2VTL contradict ion with LINEAR VOH = VDD − VDSL = VDD Check if load could have been saturated. 2 k L VTL kL 2 0= (VGSL − VTL ) = 2 22 ⇒ VTL = 0 not true because VTL < 0 Note: depletion load inverter enables VOH to reach VDD VDD Esener ECE 108 4. 11 B. TD SAT, TL LIN V TD ≤ Vin ≤ Vin * I D = I DL kd 2 (Vin − VTD ) 2 VDD 2 VDSL = k L (− VTL )VDSL − ⇒ 2 VDSL = VDD − Vout (VDD − Vout )2 + 2VTL (VDD − Vout ) + β r (Vin − VTD )2 = 0 C. TD SAT, TL SAT (Vin − VTD )2 = * Vin = VTD − kL 2 VTL 2 VTL βr Vout is NOT DEFINED for Vin*. This means that around Vin* the transfer characteristic has a slope of infinity. Depletion load inverter has a narrower transition region. Esener ECE 108 4. 12 D. TD LIN, TL SAT v in ≥ v in * 2 VDSD k L k D (Vin − VTD )VDSD − = (− VTL ) 22 v2 out − 2(Vin − VTD )v out 2 VTL + βr =0 ∆ = 0 -> v in = VTD − * VDD VTL βr -> this eq. is valid till Vin = Vin* VTL ≤ vout ≤ VDD + VTL (VTL < 0 ) βr Vout SAT VTL Vin * VTD TD OFF LIN SAT TL LiN/OFF LIN SAT Vin < VDD 1+1 βr Esener ECE 108 4. 13 4.4. Comparison of resistive, enhancement and depletion mode loads LOAD LINE ID DEPLETION RESISTIVE ENHANCEMENT VDD -V TL V DD Vout TRANSFER CHARACTERISTICS V OU Depletionn Resistive Enhancement V IN ...
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This note was uploaded on 10/24/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.

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