05''ECE108CMOSfabrication2010 - Ch. 5” CMOS Fabrication...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Ch. 5” CMOS Fabrication •Lithography •Etching •Oxidation •Doping •Deposition UCSD Esener 5”. An Overview of Microfabrication Processes • Photolithography: Process by which the surface of a substrate can be patterned with micron size features. Photolithography requires a photoresist layer to be put on the substrate, a photomask that has the required pattern and a UV light source to expose the photoresist. • The photoresist is a photographic emulsion that when exposed to UV light changes its chemical structure. For example region exposed may be cross linked and hardened. Developers exist for removing the non-hardened regions of photoresist. Photoresist is chemically resistant to chemicals that etch inorganic materials (especially buffered HF) and can be removed easily by organic removers such as acetone. • Photomask is a piece of glass with a photographic emulsion on it. When exposed to light or to e-beam the photographic emulsion turns black and absorbs the UV light. Photomasks are typically generated today by e-beam lithography machines with feature sizes down to 0.1mm. • Mask Aligner is a special instrument used to align different mask layers corresponding to different photolithographic steps on the substrate such that complex devices can be fabricated • Oxide growth is process which results in the formation of a SiO2 layer on the top of the silicon circuit. This oxide layer can be used as a mask for subsequent processing steps or can be used as an electrical component within a transistor such as the gate oxide of a MOSFET. When used as a mask its chemical properties are critical and it can be deposited by chemical vapor deposition, that is by decomposing silane gas in a reactor in an oxygen rich environment and depositing the formed SiO2 molecules on silicon typically at lower temperatures e.g. 350oC. When used as gate oxide or as an electrical insulator, the electrical properties of the SiO2 layer are critical. In that case the SiO2 layer is grown by oxidizing the silicon wafer surface by bringing it in contact with oxygen in a high temperature furnace e.g. @1100oC. • Oxide etching processes involve the removal of SiO2 layers from the surface of the silicon substrate usually using a photoresist mask to pattern the SiO2 layer. This can be done by wet etching, (by dipping the photoresist patterned substrate into buffered HF, where the acid will attack the exposed regions of SiO2 ) or by dry etching (where a chemical gas plasma will attack and etch the exposed SiO2 regions). • Doping is the process of introducing dopant atoms into silicon for creating n and p type regions. Doping can be realized by diffusion or by ion implantation. • The diffusion process involves bringing the dopant sources such as Phosphorous or Boron in close contact with the silicon substrate in a diffusion furnace at temperatures above 9000C. The dopant atoms will then diffuse into the exposed silicon regions whereas the SiO2 protected regions will not be doped. Typically the diffusion process is followed by a high temperature (1100oC) oxidation process to drive in the dopant atoms further into the substrate. • The ion implantation process uses an ion implanter that accelerates the dopant atoms in vacuum such that when they encounter the silicon substrate they have enough energy to penetrate the unprotected regions of the silicon substrate. Subsequently a higher temperature annealing (600oC) step is required to activate the dopant atoms and restore the crystal quality of the silicon surface. • Metallization is generally carried out by evaporating aluminum and depositing it on a silicon wafer. The process of evaporation is carried out in a vacuum chamber where an aluminum source is heated. The evaporating Aluminum atoms gain enough energy in vacuum to freely move in the chamber and attach themselves to cooler regions including the silicon substrates. The thin Aluminum layer can then be patterned using a photolithographic step. UCSD Esener 5”. 2 Photolithography UCSD Esener 5”. 3 Photolithography Using photolithography to pattern polysilicon with positive photoresist The process of selectively removing un-exposed (or exposed) photoresist is called development. The photoresist is patterned During etching of the desired material, patterned photoresist acts as a mask to protect desired regions of the material being etched The pattern of the original mask is transferred to the desired material by means of photolithography UCSD Esener 5”. 4 Photolithography UCSD Esener 5”. 5 Etching UCSD Esener 5”. 6 Oxidation 7 Doping by Diffusion or Ion Implantation Diffusion is done at high temperatures 800-1200C while ion implantaion can be done at low temperature 500-800C UCSD Esener 5”. 8 Deposition UCSD Esener 5”. 9 Epitaxy UCSD Esener 5”. 10 STANDARD METAL GATE MOS TRANSISTOR LAYOUT AND PROCESS Strip Field oxide Grow gate oxide, open contacts Diffuse, oxidize open gate Metallize and pattern UCSD Esener 5”. 11 UCSD STANDARD METAL GATE MOS TRANSISTOR LAYOUT AND PROCESS Strip Field oxide 1 Diffuse, oxidize open gate region 2 Grow gate oxide, open contacts 3 Metallize and pattern 4 UCSD Esener 5”. 12 UCSD pMOS process steps UCSD Esener 5”. 13 UCSD The PMOS fabrication • Around 1970, pMOS circuits with aluminum gate metal and wiring were dominant. • The primary problem at the time was threshold voltage control. Positively charged ions in the oxide decreased the threshold voltage of the devices. p-type MOSFETs were therefore the device of choice despite the lower hole mobility, since they would still be enhancement-type devices even when charge was present. • Thermal oxidation of the silicon in an oxygen or water vapor atmosphere provided a quality gate oxide with easily controlled thickness. The same process was also used to provide a hightemperature mask for the diffusion process and a passivation and isolation layer. Some people claim that the quality and versatility of silicon’s oxide made silicon the preferred semiconductor over germanium. • The oxide was easily removed in hydrofluoric acid (HF), without removing the underlying silicon, thanks to the high selectivity if the etch • Aluminum was evaporated over the whole wafer and then etched yielding both the gate metal and the metal wiring connecting the devices. A small amount of copper (~2%) was added to make the aluminum more resistant to electromigration. Electromigration is the movement of atoms due to the impact with the electrons carrying the current through the wire. This effect can cause open circuits and is therefore a well-known reliability problem. • Annealing the metal in a nitrogen/hydrogen (N2/H2) ambient was used to improve the metalsemiconductor contact and to reduce the surface state density at the semiconductor/gate-oxide interface. UCSD UCSD Esener 5”. 14 SELF ALIGNED GATE MOS TRANSISTOR LAYOUT AND PROCESS Strip Field oxide Pattern gate and oxide Diffuse Regrow gate oxide Deposit gate Metallize and pattern Oxidize and open contact holes UCSD Esener 5”. 15 UCSD SELF ALIGNED GATE MOS TRANSISTOR LAYOUT AND PROCESS Strip Field oxide & Regrow gate oxide 1 Deposit gate & pattern , diffuse 2 Oxidize and open contact holes 3 Metallize and pattern 4 UCSD Esener 5”. 16 UCSD INVERTER LAYOUT METAL GATE, SATURATED LOAD POLY-GATE, DEPLETION LOAD •Provides better noise margins •Higher speed (small Cgs and NL pull up) •More levels of interconnects-smaller area •But requires one additional mask layer and poly deposition UCSD Esener 5”. 17 UCSD Evolution to POLY gate NMOS UCSD Esener 5”. 18 UCSD Manufacturing and circuit Improvements Most changes were introduced to provide superior performance, better reliability and higher yield. Increasing the number of transistors: • Reduction of the gate length. A gate length reduction provides a shorter transit time and hence a faster device. This reduction is linked to a reduction of the minimum feature size and therefore yields smaller transistors as well as a larger number of transistors on a chip with a given size. I • Making larger chips, so that the number of transistors per chip increased even faster. • Increasing wafer size to accommodate the larger chips while reducing the loss due to partial chips at the wafer periphery. Larger wafers further reduce the cost per chip as more chips can be accommodated on a single wafer Circuit Improvements • Early on, the pMOS devices were replaced with nMOS transistors because of the better electron mobility. Enhancement-mode loads were replaced by depletion-mode loads yielding faster logic circuits with larger operating margins. UCSD Esener 5”. 19 UCSD Process Improvements aiming at circuit performance I Process improvements can be split into those aimed at improving the circuit performance and those improving the manufacturability and reliability. • Self-aligned poly-silicon gate process was introduced before CMOS and marked the beginning of modern day MOSFETs. The self-aligned structure, is obtained by using the gate as the mask for the source-drain implant. Since the crystal damage caused by the high-energy ions must be annealed at high temperature (~800 C), an aluminum gate could no longer be used. Doped poly-silicon was found to be a very convenient gate material since it withstands the high anneal temperature and can be oxidized just like silicon. • The self-aligned process lowers the parasitic capacitance between gate and drain and therefore improves the high-frequency performance and switching time. • Addition of a silicide layer on top of the gate reduces the gate resistance while still providing a quality implant mask. The self-aligned process also reduced the transistor size and hence increased the density. • Local oxidation isolation structure (LOCOS), replaced the field oxide. A Si3N4 layer is used to prevent the oxidation in the MOSFET region. This oxide provides an implant mask and contact hole mask yielding an even more compact device. UCSD Esener 5”. 20 UCSD Process Improvements aimed at manufacturability and reliability: • Chemical vapor deposition (CVD) of insulating layers replaced thermal oxidation since it does not consume the underlying silicon andbecause there is no limit to the obtainable thickness since materials other than SiO2 (for instance Si3N4) can be deposited. • Ion implantation replaced diffusion because of its superior control and uniformity. • Dry etching including plasma etching, reactive ion etching (RIE) and ion beam etching has replaced wet chemical etching. These etch processes provide better etch rate uniformity and control as well as very pronounced anisotropic etching. • Sputtering of metals has completely replaced evaporation. Sputtering typically provides better adhesion and thickness control. • Deuterium anneal is a recent modification of the standard hydrogen anneal, which passivates the surface states. The use of deuterium therefore reduces the increase of the surface state density due to hot-electron impact. UCSD Esener 5”. 21 UCSD CMOS INVERTER & LAYOUT VDD CMOS circuits have a lower power dissipation and larger operating margin. It was only when the number of transistors per chip became much larger that the In inherent advantages of CMOS circuits became clear. PMOS Out NMOS 22 CMOS Improvements The key circuit improvement is the use of CMOS circuits, containing both nMOS and pMOS transistors. • CMOS circuits was first introduced by RCA but did not immediately catch on since the logic circuits were somewhat slower and larger than the then-dominant nMOS depletion logic. • It was only when the number of transistors per chip became much larger that the inherent advantages of CMOS circuits became clear. CMOS circuits have a lower power dissipation and larger operating margin. They became the technology of choice as thousands of devices were integrated on a single chip. • Today, the CMOS technology is the dominant technology in the IC industry as the tenfold reduction of power dissipation largely outweighs the 30%-50% speed reduction and size increase. Wiring: • Multilevel wiring is a necessity when one increases the number of transistors per chip. The number of wires increases with the square of the number of transistors and the average wire length increase linearly with the chip size. The multilevel wiring has increasingly become a bottleneck in the fabrication of high-performance circuits. • Planarization techniques, and the introduction of copper instead of aluminumbased metals have further increased the wiring density and lowered the wiring resistance UCSD Esener 5”. 23 UCSD Inverter Cross-section • Typically use p-type substrate for nMOS transistors • Requires n-well for body of pMOS transistors A GND VDD Y SiO2 n+ diffusion n+ n+ p+ p+ n well p substrate nMOS transistor p+ diffusion polysilicon metal1 pMOS transistor UCSD Esener 5”. 24 Well and Substrate Taps • Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode) • Use heavily doped well and substrate contacts / taps A GND VDD Y p+ n+ n+ p+ p+ n+ n well p substrate substrate tap well tap UCSD Esener 5”. 25 Inverter Mask Set • Transistors and wires are defined by masks • Cross-section taken along dashed line A Y GND VDD nMOS transistor substrate tap pMOS transistor well tap UCSD Esener 5”. 26 Detailed Mask Views • Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal n well Polysilicon n+ Diffusion p+ Diffusion Contact Metal UCSD Esener 5”. 27 Fabrication Steps • Start with blank wafer • Build inverter from the bottom up • First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 p substrate UCSD Esener 5”. 28 Oxidation • Grow SiO2 on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace SiO2 p substrate UCSD Esener 5”. 29 Photoresist • Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light Photoresist SiO2 p substrate UCSD Esener 5”. 30 Lithography • Expose photoresist through n-well mask • Strip off exposed photoresist Photoresist SiO2 p substrate UCSD Esener 5”. 31 Etch • Etch oxide with hydrofluoric acid (HF) • Only attacks oxide where resist has been exposed Photoresist SiO2 p substrate UCSD Esener 5”. 32 Strip Photoresist • Strip off remaining photoresist • Necessary so resist doesn’t melt in next step SiO2 p substrate UCSD Esener 5”. 33 n-well • • • n-well is formed with diffusion or ion implantation Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si SiO2 n well UCSD Esener 5”. 34 Strip Oxide • Strip off the remaining oxide using HF • Back to bare wafer with n-well • Subsequent steps involve similar series of steps n well p substrate UCSD Esener 5”. 35 Polysilicon • Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor Polysilicon Thin gate oxide n well p substrate UCSD Esener 5”. 36 Polysilicon Patterning • Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide n well p substrate UCSD Esener 5”. 37 N-diffusion • Use oxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact n well p substrate UCSD Esener 5”. 38 N-diffusion (cont.) • Pattern oxide and form n+ regions n+ Diffusion n well p substrate UCSD Esener 5”. 39 N-diffusion (cont.) • Historically dopants were diffused • Usually ion implantation today • But regions are still called diffusion n+ n+ n+ n well p substrate UCSD Esener 5”. 40 N-diffusion (cont.) • Strip off oxide to complete patterning step n+ n+ n+ n well p substrate UCSD Esener 5”. 41 Slide P-Diffusion • Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ n well p substrate UCSD Esener 5”. 42 Contacts • Now we need to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed Contact Thick field oxide p+ n+ n+ p+ p+ n+ n well p substrate UCSD Esener 5”. 43 Metalization • Sputter on aluminum over whole wafer • Pattern to remove excess metal, leaving wires M e ta l Metal Thick field oxide p+ n+ n+ p+ p+ n+ n well p substrate UCSD Esener 5”. 44 Modern CMOS Cross-section Silicide Silicide n+ Poly STI n+ Source-drain extensions Gate oxide n+ p-doping Shallow Trench Isoation p+ Poly p+ p+ n-doping n-well STI Source-drain extensions UCSD Esener 5”. 45 UCSD Summary of CMOS Fabrication UCSD Esener 5”. 46 N-well CMOS fab. process UCSD Esener 5”. 47 TEM Cross-section UCSD Esener 5”. 48 ...
View Full Document

This note was uploaded on 10/24/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.

Ask a homework question - tutors are online