06ECE108Ch6MOSLogicpresentation (1)

06ECE108Ch6MOSLogicpresentation (1) - MOS LOGIC Chapter 6...

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MOS LOGIC Chapter 6 1 ECE108 UCSD Esener
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Esener UCSD Ch. 6. V DD V OUT GND X a X b X c 3-INPUT NOR V DD V OUT GND X a X b X c 3-INPUT NAND 2-T PULL-UP MOS LOGIC GATES 6.1. NMOS NOR and NAND GATES 2
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Esener UCSD Ch. 6. 6.2 COMPOSITE 2T PULL-UP MOS LOGIC GATES V DD Y=X 1 (X 2 X 3 +X 4 X 5 ) X1 X2 X3 X5 X4 RULE: Express logic function as the complement of sum of products Synthesize each product as a serial combination of driver transistors 3
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Esener UCSD Ch. 6. 4 Worst case b r calculation V DD X1 X2 X3 X5 X4 (W/L) pu =1/3 (W/L) pdi =3; i=(1;5) Worst case condition occurs when X1=X2=X3=1 and X4=X5=0 or X1=X4=X5=1 and X2=X3=0 Worst case (W/L) pdeff = 1 3 1 ) / ( - i W L (W/L) wc pdeff = 1 Worst case b r = 3 Note: best case X1=X2=X3=X4=X5 [ ] 1 1 1 1 1 5 4 1 3 2 ) / ( ) / ( ) / ( - - - - - + + W L W L W L i i Best case (W/L) pdeff = (W/L) 2;5 = ((3/2)+(3/2)) -1 = 3 Best case (W/L) pdeff = [(1/3)+(1/3) ] -1 =3/2 => β r=9/2
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Esener UCSD Ch. 6. V DD Q A A B C A A C B B Q C GND AN EXAMPLE OF COMPOSITE LOGIC ADDER CIRCUIT Implemented with depletion pull-up technology 5
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Esener UCSD Ch. 6.
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This note was uploaded on 10/24/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.

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06ECE108Ch6MOSLogicpresentation (1) - MOS LOGIC Chapter 6...

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