08ECE108Ch8Moslogicpasstranspresentation

08ECE108Ch8Moslogicpasstranspresentation - ECE108 ESENER 8....

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Unformatted text preview: ECE108 ESENER 8. 1 8. NON RESTORING MOS LOGIC ___________________________________________________________________________________________________________ 8.1. Pass Transistor V = V or V = 0 G DD G A V B D S S D • Use MOSFET like a switch • Takes advantage of MOS symmetry • Reduces transistor count But • Is non-regenerative • Introduces signal loss Esener ECE 108 8.2. 8. 2 Pass Transistor Operation modes __________________________________________________________________ − VG = VDD => transistor on for VG - VB > VT ⇒ V B ˜ V A VDD a) V A = V DD ⇒ Solve as enhancement load inverter V DD b) V A = 0 ⇒ A B S c) 0 <VA<VDD⇒ D Solve like CMOS H to L transition VA=VB=0 VA Solve like linear/saturated load device VB VDD− V B − V T < VA − VB ⇒ SAT V DD VDD− VB −VT > VA − VB ⇒ LIN VG = 0 => transistor off (VA and VB are independent) Esener ECE 108 LINEAR PULL-UP / PASS TRANSISTOR IN LINEAR MODE For linear VGG > VDD + VTL(VDD) VGS = VGG -VO 8. 3 Esener ECE 108 PASS TRANSISTOR APPLICATION EXAMPLES 8. 4 Esener ECE 108 8. 5 8.3. TRANSMISSION GATES __________________________________________________________________________ How can we prevent the VT drop across a pass transistor? V G = V DD and VG=0 VG A) V A = V DD V B = 0 Initial conditions => PMOS on, NMOS on until VB = VA - VT PMOS on until VA = VB B) V A = V DD V B = V DD ⇒ PMOS on, NMOS off C) VA = 0 VB = V0 ⇒ Both transistors are LIN/OFF D) V A = 0 V B = V DD ⇒ PMOS on until VB = VT, NMOS on NMOS on VB < VT => V G = 0 and V G = V DD Both transistors are off VB = VA = 0 VA S1 D2 V DD D1 S2 VB D1 S1 S2 D2 VG Esener ECE 108 8. 6 8.4. Conductance of a Pass-Transistor and Transmission Gate _________________________________________________________________ Vc Vo sin ω t G Vo sinω t + Vdc D G(Vdc ) +Vdc S C C What is G(Vdc ) ω ω= G(Vdc ) C Assume Linear op. V DS = VDG + VGS = Vdc − VC + VGS ⇒ VGS = VC + V DS − Vdc V 2 I D = k (VC − Vdc + V DS − VT )V DS − DS 2 G= δ ID 2V = k (Vc − Vdc + VDS − VT ) + VDS − DS δ VDS Vdc 2 G= δ ID = k(Vc − Vdc − VT ) δ VDS G = − kVdc + k(Vc − VT ) * Linear drop with Vdc. Slope – k * Linear shift with VC Esener ECE 108 8. 7 Resistance of Transmission Gate 30000.0 Rn (W/L) p=(W/L) n = 1.8/1.2 R (O m) h 20000.0 Rp 10000.0 0.0 0.0 R eq 1.0 2.0 3.0 4.0 Vout Assuming both transistors linear Geq=kn(VDD-VTn)+kp(VDD-|VTp|) As first order approximation Geq can be assumed constant 5.0 Esener ECE 108 8. 8 Transmission gate Based Multiplexer S S A S S S In2 VDD VDD M 2 F S M 1 B S F=AS+BS’ GND In1 Esener ECE 108 8. 9 Transmission Gate XOR B B=1 => M1/M2 inverter M3/M4 off ⇒F=A’B B=0 => M1/M2 disabled =>F=AB’ Combination: XOR Note: F always path to VDD or GND F B M2 A A F M1 M3/M4 B B Esener ECE 108 8. 10 Robust pass transistor design: Level Restoring Transistor Transmission gate can be area inefficient. Solution pass-transistor with level restoration Vout (V) 5.0 V DD 3.0 V DD Level Restorer B Mn with VB 1.0 Mr A without -1.00 M2 2 t (nsec) 4 6 (a) Output node X Out without 3.0 VX M1 with 5.0 Advantage: Full Swing Disadvantage: More Complex, Larger Capacitance Sizing Mr: Writability problem 1.0 -1.00 2 4 t (nsec) (b) Intermediate node X 6 ...
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This note was uploaded on 10/24/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.

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